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MC74HC132ADR2 PDF预览

MC74HC132ADR2

更新时间: 2024-01-27 15:53:44
品牌 Logo 应用领域
安森美 - ONSEMI 触发器逻辑集成电路光电二极管
页数 文件大小 规格书
8页 151K
描述
Quad 2-Input NAND Gate with Schmitt-Trigger Inputs

MC74HC132ADR2 技术参数

是否无铅: 不含铅生命周期:Active
零件包装代码:SOIC包装说明:SOP, SOP14,.25
针数:14Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:0.51
系列:HC/UHJESD-30 代码:R-PDSO-G14
JESD-609代码:e3长度:8.65 mm
负载电容(CL):50 pF逻辑集成电路类型:NAND GATE
最大I(ol):0.004 A湿度敏感等级:1
功能数量:4输入次数:2
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP14,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TR
峰值回流温度(摄氏度):260电源:2/6 V
Prop。Delay @ Nom-Sup:38 ns传播延迟(tpd):190 ns
认证状态:Not Qualified施密特触发器:YES
座面最大高度:1.75 mm子类别:Gates
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:3.9 mm
Base Number Matches:1

MC74HC132ADR2 数据手册

 浏览型号MC74HC132ADR2的Datasheet PDF文件第2页浏览型号MC74HC132ADR2的Datasheet PDF文件第3页浏览型号MC74HC132ADR2的Datasheet PDF文件第4页浏览型号MC74HC132ADR2的Datasheet PDF文件第5页浏览型号MC74HC132ADR2的Datasheet PDF文件第6页浏览型号MC74HC132ADR2的Datasheet PDF文件第7页 
High–Performance Silicon–Gate CMOS  
The MC74HC132A is identical in pinout to the LS132. The device  
inputs are compatible with standard CMOS outputs; with pullup  
resistors, they are compatible with LSTTL outputs.  
The HC132A can be used to enhance noise immunity or to square up  
slowly changing waveforms.  
http://onsemi.com  
MARKING  
DIAGRAMS  
14  
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2.0 to 6.0 V  
Low Input Current: 1.0 µA  
High Noise Immunity Characteristic of CMOS Devices  
PDIP–14  
N SUFFIX  
CASE 646  
MC74HC132AN  
AWLYYWW  
1
14  
SOIC–14  
D SUFFIX  
CASE 751A  
HC132A  
AWLYWW  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
1
Chip Complexity: 72 FETs or 18 Equivalent Gates  
LOGIC DIAGRAM  
A
= Assembly Location  
WL or L = Wafer Lot  
YY or Y = Year  
1
A1  
WW or W = Work Week  
3
Y1  
2
PIN ASSIGNMENT  
B1  
A1  
B1  
1
2
14  
13 B4  
12  
V
CC  
4
A2  
6
Y1  
A2  
3
4
A4  
Y2  
11 Y4  
10 B3  
5
B2  
B2  
Y2  
5
6
7
Y = AB  
9
9
8
A3  
Y3  
A3  
GND  
8
Y3  
10  
B3  
12  
A4  
11  
ORDERING INFORMATION  
Y4  
Device  
Package  
PDIP–14  
SOIC–14  
SOIC–14  
Shipping  
13  
B4  
MC74HC132AN  
MC74HC132AD  
MC74HC132ADR2  
2000 / Box  
55 / Rail  
PIN 14 = V  
PIN 7 = GND  
CC  
2500 / Reel  
FUNCTION TABLE  
Inputs  
Output  
A
B
Y
L
L
H
H
L
H
L
H
H
H
L
H
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
March, 2000 – Rev. 7  
MC74HC132A/D  

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