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MC74F256DD

更新时间: 2024-11-25 13:11:19
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摩托罗拉 - MOTOROLA 触发器锁存器逻辑集成电路光电二极管双倍数据速率
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MC74F256DD 数据手册

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MC54/74F256  
DUAL 4-BIT  
ADDRESSABLE LATCH  
TheMC54/74F256dualaddressablelatchhasfourdistinctmodesofopera-  
tion which are selectable by controlling the Clear and Enable inputs (see  
Function Table). In the addressable latch mode, data at the Data (D) inputs  
is written into the addressed latches. The addressed latches will follow the  
Data input with all unaddressed latches remaining in their previous states.  
In the memory mode, all latches remain in their previous states and are un-  
affected by the Data or Address inputs. To eliminate the possibility of entering  
erroneousdata in the latches, the enable should be held HIGH (inactive)while  
the address lines are changing. In the dual 1-of-4 decoding or demultiplexing  
mode (MR = E = LOW), addressed outputs will follow the level of the D inputs  
with all other outputs LOW. In the clear mode, all outputs are LOW and unef-  
fected by the Address and Data inputs.  
DUAL 4-BIT  
ADDRESSABLE LATCH  
FAST SCHOTTKY TTL  
J SUFFIX  
CERAMIC  
CASE 620-09  
Combines Dual Demultiplexer and 8-Bit Latch  
Serial-to-Parallel Capability  
Output from Each Storage Bit Available  
16  
1
Random (Addressable) Data Entry  
Easily Expandable  
Common Clear Input  
Useful as Dual 1-of-4 Active HIGH Decoder  
N SUFFIX  
PLASTIC  
CASE 648-08  
16  
CONNECTION DIAGRAM  
1
V
MR  
15  
E
D
Q
Q
Q
Q
0b  
CC  
16  
b
3b  
12  
2b  
11  
1b  
10  
14  
13  
9
D SUFFIX  
SOIC  
CASE 751B-03  
16  
1
ORDERING INFORMATION  
1
2
3
4
5
6
8
7
MC54FXXXJ  
MC74FXXXN Plastic  
MC74FXXXD SOIC  
Ceramic  
A
A
D
Q
Q
Q
Q
3a  
GND  
0
1
a
0a  
1a  
2a  
FUNCTION TABLE  
Inputs  
Outputs  
Operating Mode  
MR  
E
D
A
A
Q
Q
Q
Q
3
0
1
0
1
2
LOGIC SYMBOL  
Master Reset  
L
H
X
X
X
L
L
L
L
3
13  
L
L
L
L
L
L
L
L
d
d
d
d
L
H
L
L
L
H
H
Q=d  
L
Q=d  
L
L
L
Q=d  
L
L
L
L
Demultiplex (Active  
HIGH Decoder when  
D = H)  
L
L
L
D
D
b
a
A
E
14  
15  
1
2
0
H
L
Q=d  
A
MR  
Store (Do Nothing)  
H
H
X
X
X
q
0
q
q
2
q
3
1
1
1
Q
Q
Q
Q
Q
Q
Q
Q
0a 1a 2a 3a 0b 1b 2b 3b  
H
H
H
H
L
L
L
L
d
d
d
d
L
H
L
L
L
H
H
Q=d  
q
q
2
q
2
q
3
q
3
q
3
Addressable  
Latch  
q
0
q
0
q
0
Q=d  
4
5
6
7
9
10 11 12  
q
1
q
1
Q=d  
H
q
2
Q=d  
H = HIGH Voltage Level Steady State  
L = LOW Voltage Level Steady State  
X = Immaterial  
d = HIGH or LOW Data one setup time prior to the LOW-to-HIGH Enable transition.  
q = Lower case letters indicate the state of the referenced output established during the last cycle  
in which it was addressed or cleared.  
FAST AND LS TTL DATA  
4-123  

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