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MC74ACT175DR2 PDF预览

MC74ACT175DR2

更新时间: 2024-11-14 21:11:51
品牌 Logo 应用领域
安森美 - ONSEMI 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
6页 182K
描述
ACT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, SOIC-16

MC74ACT175DR2 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP16,.25
针数:16Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.4
系列:ACTJESD-30 代码:R-PDSO-G16
JESD-609代码:e0长度:9.9 mm
负载电容(CL):50 pF逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:145000000 Hz最大I(ol):0.024 A
位数:4功能数量:1
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
传播延迟(tpd):12 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:3.9 mm最小 fmax:145 MHz
Base Number Matches:1

MC74ACT175DR2 数据手册

 浏览型号MC74ACT175DR2的Datasheet PDF文件第2页浏览型号MC74ACT175DR2的Datasheet PDF文件第3页浏览型号MC74ACT175DR2的Datasheet PDF文件第4页浏览型号MC74ACT175DR2的Datasheet PDF文件第5页浏览型号MC74ACT175DR2的Datasheet PDF文件第6页 
QUAD D FLIP-FLOP  
WITH MASTER RESET  
The MC74AC/ACT175 is a high-speed quad D flip-flop. The device is useful for  
general flip-flop requirements where clock and clear inputs are common. The  
information on the D inputs is transferred to storage during the LOW-to-HIGH clock  
transition. The device has a Master Reset to simultaneously clear all flip-flops, when  
MR is low.  
The MC74AC/ACT175 consists of four edge-triggered D flip-flops with individual  
D inputs and Q and Q outputs. The Clock (CP) and Master Reset (MR) are common  
to all flip-flops. Each D input’s state is transferred to the corresponding flip-flop’s  
output following the LOW-to-HIGH Clock (CP) transition. A LOW input to the Master  
Reset (MR) will force all Q outputs LOW and Q outputs HIGH independent of Clock  
or Data inputs. The MC74AC/ACT175 is useful for applications where the Clock and  
Master Reset are common to all storage elements.  
N SUFFIX  
CASE 648-08  
PLASTIC  
Outputs Source/Sink 24 mA  
• ′ACT175 Has TTL Compatible Inputs  
Pinout: 16-Lead Packages (Top View)  
V
Q
Q
D
D
Q
Q
2
CP  
9
CC  
3
3
3
2
2
D SUFFIX  
CASE 751B-05  
PLASTIC  
16  
15  
14  
13  
12  
11  
10  
PIN NAMES  
D
CP  
MR  
Q
Q
– D  
Data Inputs  
0
3
Clock Pulse Input  
Master Reset Input  
Outputs  
– Q  
– Q  
0
0
3
3
Outputs  
1
2
3
4
5
6
7
8
MR  
Q
Q
D
D
Q
Q
1
GND  
0
0
0
1
1
LOGIC SYMBOL  
TRUTH TABLE  
Inputs  
Outputs  
D
D
Q
D
D
0
1
2
1
3
1
MR  
CP  
D
Qn  
Qn  
CP  
L
H
H
H
X
X
H
L
L
H
L
H
L
H
MR  
Q
Q
Q
Q
Q
Q
Q
3
0
0
2
2
3
L
X
Qn  
Qn  
H = HIGH Voltage Level  
L = LOW Voltage Level  
X = Immaterial  
= LOW-to-HIGH Transition of Clock  
FACT DATA  
5-1  

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