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MC74AC113N PDF预览

MC74AC113N

更新时间: 2024-09-14 22:46:23
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
6页 188K
描述
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

MC74AC113N 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP14,.3
针数:14Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.92
Is Samacsys:N系列:AC
JESD-30 代码:R-PDIP-T14JESD-609代码:e0
长度:18.86 mm负载电容(CL):50 pF
逻辑集成电路类型:J-K FLIP-FLOP最大频率@ Nom-Sup:125000000 Hz
最大I(ol):0.024 A位数:2
功能数量:2端子数量:14
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP14,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3/5 V
传播延迟(tpd):13 ns认证状态:Not Qualified
座面最大高度:4.69 mm子类别:FF/Latches
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:NEGATIVE EDGE
宽度:7.62 mm最小 fmax:125 MHz
Base Number Matches:1

MC74AC113N 数据手册

 浏览型号MC74AC113N的Datasheet PDF文件第2页浏览型号MC74AC113N的Datasheet PDF文件第3页浏览型号MC74AC113N的Datasheet PDF文件第4页浏览型号MC74AC113N的Datasheet PDF文件第5页浏览型号MC74AC113N的Datasheet PDF文件第6页 
DUAL JK NEGATIVE  
EDGE-TRIGGERED  
FLIP-FLOP  
The MC74AC113/74ACT113 consists of two high-speed completely independent  
transition clocked JK flip-flops. The clocking operation is independent of rise and fall  
times of the clock waveform. The JK design allows operation as a D flip-flop (refer to  
MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.  
Asynchronous Inputs:  
LOW input to S (Set) sets Q to HIGH level  
D
Set is independent of clock  
Outputs Source/Sink 24 mA  
• ′ACT113 Has TTL Compatible Inputs  
N SUFFIX  
CASE 646-06  
PLASTIC  
CONNECTION DIAGRAM  
V
CP  
K
J
S
Q
Q
CC  
2
2
2
D2  
10  
2
2
8
14  
13  
12  
11  
9
D SUFFIX  
CASE 751A-03  
PLASTIC  
J
Q
Q
S
D
CP  
K
K
J
Q
Q
CP  
S
D
LOGIC SYMBOL  
1
2
3
4
5
6
7
CP  
K
J
S
Q
Q
GND  
4
10  
1
1
1
D1  
1
1
S
S
D
D
MODE SELECT — TRUTH TABLE  
3
J
Q
Q
5
6
11  
J
Q
Q
9
Inputs  
Outputs  
1
2
CP  
K
13  
12  
CP  
K
Operating Mode  
S
D
J
K
Q
Q
8
Set  
Toggle  
Load “0” (Reset)  
Load “1” (Set)  
Hold  
L
X
h
l
h
l
X
h
h
l
H
q
L
H
q
L
q
H
L
q
H
H
H
H
V
= PIN 14  
CC  
GND = PIN 7  
l
H, h = HIGH Voltage Level  
L, l = LOW Voltage Level  
X = Don’t Care  
l, h (q) = Lower case letters indicate the state of the referenced input  
(oroutput) one set-up time prior to the HIGH to LOW clock transition.  
FACT DATA  
5-1  

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