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MC7447AVS1000LB PDF预览

MC7447AVS1000LB

更新时间: 2024-02-09 23:13:03
品牌 Logo 应用领域
恩智浦 - NXP 时钟外围集成电路
页数 文件大小 规格书
56页 1285K
描述
RISC Microprocessor Hardware Specifications

MC7447AVS1000LB 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:LGA包装说明:25 X 25 MM, 2.20 MM HEIGHT, 1.27 MM PITCH, ROHS COMPLIANT, CERAMIC, LGA-360
针数:360Reach Compliance Code:not_compliant
ECCN代码:3A991HTS代码:8542.31.00.01
风险等级:5.7其他特性:ALSO REQUIRES 1.8V OR 2.5V SUPPLY
地址总线宽度:36位大小:32
边界扫描:YES最大时钟频率:167 MHz
外部数据总线宽度:64格式:FLOATING POINT
集成缓存:YESJESD-30 代码:S-CBGA-X360
长度:25 mm低功率模式:YES
湿度敏感等级:1端子数量:360
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:CGA
封装等效代码:LGA360,19X19,50封装形状:SQUARE
封装形式:GRID ARRAY峰值回流温度(摄氏度):260
电源:1.3,1.8/2.5 V认证状态:Not Qualified
座面最大高度:2.2 mm速度:1000 MHz
子类别:Microprocessors最大供电电压:1.35 V
最小供电电压:1.25 V标称供电电压:1.3 V
表面贴装:YES技术:CMOS
端子形式:UNSPECIFIED端子节距:1.27 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:40
宽度:25 mmuPs/uCs/外围集成电路类型:MICROPROCESSOR, RISC
Base Number Matches:1

MC7447AVS1000LB 数据手册

 浏览型号MC7447AVS1000LB的Datasheet PDF文件第7页浏览型号MC7447AVS1000LB的Datasheet PDF文件第8页浏览型号MC7447AVS1000LB的Datasheet PDF文件第9页浏览型号MC7447AVS1000LB的Datasheet PDF文件第11页浏览型号MC7447AVS1000LB的Datasheet PDF文件第12页浏览型号MC7447AVS1000LB的Datasheet PDF文件第13页 
Electrical and Thermal Characteristics  
Table 2. Absolute Maximum Ratings (continued)  
1
Characteristic  
Symbol Maximum Value Unit Notes  
–55 to 150 °C  
Storage temperature range  
T
stg  
Notes:  
1. Functional and tested operating conditions are given in Table 4. Absolute maximum ratings are stress ratings only, and  
functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause  
permanent damage to the device.  
2. Caution: V /AV must not exceed OV by more than 1.0 V during normal operation; this limit may be exceeded for a  
DD  
DD  
DD  
maximum of 20 ms during the power-on reset and power-down sequences.  
3. Caution: OV must not exceed V /AV by more than 2.0 V during normal operation; this limit may be exceeded for a  
DD  
DD  
DD  
maximum of 20 ms during the power-on reset and power-down sequences.  
4. BVSEL must be set to 0, such that the bus is in 1.8-V mode.  
5. BVSEL must be set to HRESET or 1, such that the bus is in 2.5-V mode.  
6. Caution: V must not exceed OV by more than 0.3 V at any time including during power-on reset.  
in  
DD  
7. V may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.  
in  
Figure 2 shows the undershoot and overshoot voltage on the MPC7447A.  
OV + 20%  
DD  
OV + 5%  
DD  
OV  
DD  
V
IH  
V
IL  
GND  
GND – 0.3 V  
GND – 0.7 V  
Not to Exceed 10%  
of t  
SYSCLK  
Figure 2. Overshoot/Undershoot Voltage  
The MPC7447A provides several I/O voltages to support both compatibility with existing systems and  
migration to future systems. The MPC7447A core voltage must always be provided at the nominal voltage  
(see Table 4) or at the supported derated voltage (see Section 5.3, “Voltage and Frequency Derating”). The  
input voltage threshold for each bus is selected by sampling the state of the voltage select pins at the  
negation of the signal HRESET. The output voltage will swing from GND to the maximum voltage applied  
to the OV power pins. Table 3 provides the input threshold voltage settings. Because these settings may  
DD  
change in future products, it is recommended that BVSEL be configured using resistor options, jumpers,  
or some other flexible means, with the capability to reconfigure the termination of this signal in the future  
if necessary.  
MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5  
10  
Freescale Semiconductor  

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