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MC44460B

更新时间： 2024-11-14 22:39:59
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 消费电路商用集成电路叠加集成电路电视光电二极管信息通信管理控制器
页数 文件大小 规格书
16页 442K
描述
PICTURE-IN-PICTURE (PIP) CONTROLLER

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中文翻译

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MC44460B 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DIP包装说明：SDIP, SDIP56,.6
针数：56Reach Compliance Code：unknown
风险等级：5.89应用：TV
商用集成电路类型：PICTURE-IN-PICTURE IC锁定直播画面：YES
JESD-30 代码：R-PDIP-T56JESD-609代码：e0
长度：52.07 mm功能数量：1
端子数量：56封装主体材料：PLASTIC/EPOXY
封装代码：SDIP封装等效代码：SDIP56,.6
封装形状：RECTANGULAR封装形式：IN-LINE, SHRINK PITCH
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
认证状态：Not Qualified座面最大高度：5.08 mm
子类别：Superimposer ICs最大压摆率：160 mA
最大供电电压 (Vsup)：5 V最小供电电压 (Vsup)：5 V
表面贴装：NO技术：BICMOS
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：1.778 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED视频标准：NTSC
宽度：15.24 mmBase Number Matches：1

MC44460B 数据手册

 浏览型号MC44460B的Datasheet PDF文件第2页浏览型号MC44460B的Datasheet PDF文件第3页浏览型号MC44460B的Datasheet PDF文件第4页浏览型号MC44460B的Datasheet PDF文件第5页浏览型号MC44460B的Datasheet PDF文件第6页浏览型号MC44460B的Datasheet PDF文件第7页 
Order this document by MC44460/D  
PICTURE–IN–PICTURE  
(PIP) CONTROLLER  
The MC44460 Picture–in–Picture (PIP) controller is a low cost member of  
a family of high performance PIP controllers and video signal processors for  
television. It is NTSC compatible and contains all the analog signal  
processing, control logic and memory necessary to provide for the overlay of  
a small picture from a second non synchronized source onto the main picture  
of a television. All control and setup of the MC44460 is via a standard two pin  
SEMICONDUCTOR  
TECHNICAL DATA  
2
I C bus interface. The device is fabricated using BICMOS technology. It is  
available in a 56–pin shrink dip (SDIP) package.  
The main features of the MC44460 are:  
• Two NTSC CVBS Inputs  
• Switchable Main and PIP Video Signals  
• Single NTSC CVBS Output Allows Simple TV Chassis Integration  
• Two PIP Sizes; 1/16 and 1/9 Screen Area  
• Freeze Field Feature  
56  
1
• Variable PIP Position in 64–X by 64–Y Steps  
• PIP Border with Programmable Color  
• Programmable PIP Tint and Saturation Control  
• Automatic Main to PIP Contrast Balance  
• Vertical Filter  
B SUFFIX  
PLASTIC PACKAGE  
CASE 859  
(SDIP)  
• Integrated 64 k Bit DRAM Memory Resulting in Minimal RFI  
• Minimal RFI Allows Simple Low Cost Application into TV  
• I C Bus Control – No External Variable Adjustments Needed  
• Operates from a Single 5.0 V Supply  
• Economical 56–Pin Shrink DIP Package  
ORDERING INFORMATION  
Operating  
2
Temperature Range  
Device  
Package  
MC44460B  
T
J
= –65° to +150°C  
SDIP  
Representative Block Diagram  
Decoder Clamp Caps  
Sync Out  
28  
Filter PLL  
ADC Mid–Ref  
51  
33  
40  
41  
42  
29  
Filter  
Tracking  
Sync In  
H PLL  
Low Pass  
Filter  
36  
34  
H and V  
Timebase  
31  
32  
Video 1  
Video 2  
Input  
Switch  
503 kHz Res  
Band Pass  
Filter  
Y
Y
Y
U V  
6–Bit  
ADC  
37  
49  
NTSC  
Decoder  
1
2
3
4
5
Decoder ACC  
Main Out  
V
U
V
U
Clamp  
6
H
in  
3
V
in  
PIP  
Switch  
SCL  
Digital  
Logic  
6
57.28 MHz  
0
°
90°  
38  
39  
7
Tint DAC  
Sat DAC  
SDA  
Reset  
Vert  
Decoder Xtal  
Decoder PLL  
4X S/C  
Osc + PLL  
14.32 MHz  
6
10  
30  
Vid 1/2 Sel  
Multi Test  
16 F  
SC  
PLL  
6
16X S/C  
Osc + PLL  
44  
45  
NTSC  
Encoder  
3.0 MHz  
LPF  
Encoder Phase  
Encoder ACC  
U DAC  
V DAC  
Y DAC  
Clamp  
3.0 MHz  
LPF  
0°  
90°  
6
Memory  
8.0 k x 8  
DRAM  
Y
U
V
4X S/C  
Osc + PLL  
I Ref  
3.0 MHz  
LPF  
6
46  
47  
52 53 54  
6
Encoder  
PLL  
Encoder  
Xtal  
Cur Ref  
Encoder Clamp Caps  
This device contains 500,000 active transistors.  
This document contains information on a new product. Specifications and information herein  
are subject to change without notice.  
Motorola, Inc. 1996  
1234567...16

中文翻译

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