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MC145564 PDF预览

MC145564

更新时间: 2024-02-06 07:36:48
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA PC
页数 文件大小 规格书
20页 345K
描述
PCM Codec-Filter

MC145564 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP20,.3Reach Compliance Code:unknown
风险等级:5.91Is Samacsys:N
压伸定律:MU-LAW滤波器:YES
最大增益公差:0.25 dBJESD-30 代码:R-PDIP-T20
JESD-609代码:e0线性编码:NOT AVAILABLE
负电源额定电压:-5 V功能数量:1
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP20,.3
封装形状:RECTANGULAR封装形式:IN-LINE
电源:+-5 V认证状态:Not Qualified
子类别:Codecs最大压摆率:12 mA
标称供电电压:5 V表面贴装:NO
技术:CMOS电信集成电路类型:PCM CODEC
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUALBase Number Matches:1

MC145564 数据手册

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serial PCM word, clocked by BCLK , out of D . If the FS  
X
VPO+  
X
X
pulse is high for more than eight BCLK periods, the D and  
Voltage Power Output (Non–Inverted)  
(MC145554/67 Only)  
X
X
TS outputs will remain in a low–impedance state until FS  
is brought low. The length of the FS pulse is used to deter-  
X
X
X
This non–inverted output of the receive push–pull power  
amplifier pair can drive 300 to 3.3 V peak.  
mine whether the transmit and receive digital I/O conforms to  
the Short Frame Sync or to the Long Frame Sync conven-  
tion.  
POWER SUPPLY  
GNDA  
Analog Ground  
TS  
X
Transmit Time Slot Indicator  
This terminal is the reference level for all signals, both ana-  
log and digital. It is 0 V.  
This is an open–drain output that goes low whenever the  
D
output is in a low–impedance state (i.e., during the trans-  
X
V
mit time slot when the PCM word is being output) for en-  
abling a PCM bus driver.  
CC  
Positive Power Supply  
V
is typically 5 V.  
CC  
ANLB  
V
BB  
Negative Power Supply  
Analog Loopback Control Input (MC145564/67 Only)  
When held high, this pin causes the input of the transmit  
V
is typically – 5 V.  
BB  
RC active filter to be disconnected from GS and connected  
X
to VPO+ for analog loopback testing. This pin is held low in  
normal operation.  
FUNCTIONAL DESCRIPTION  
ANALOG INTERFACE AND SIGNAL PATH  
The transmit portion of these codec–filters includes a low–  
noise gain setting amplifier capable of driving a 600 load.  
Its output is fed to a three–pole anti–aliasing pre–filter. This  
pre–filter incorporates a two–pole Butterworth active low–  
pass filter, and a single passive pole. This pre–filter is fol-  
lowed by a single ended–to–differential converter that is  
clocked at 256 kHz. All subsequent analog processing uti-  
lizes fully differential circuitry. The next section is a fully–dif-  
ferential, five–pole switched capacitor low–pass filter with a  
3.4 kHz passband. After this filter is a 3–pole switched–ca-  
pacitor high–pass filter having a cutoff frequency of about  
200 Hz. This high–pass stage has a transmission zero at dc  
that eliminates any dc coming from the analog input or from  
accumulated operational amplifier offsets in the preceding fil-  
ter stages. The last stage of the high–pass filter is an auto-  
zeroed sample and hold amplifier.  
ANALOG  
GS  
X
Gain–Setting Transmit  
This output of the transmit gain–adjust operational amplifi-  
er is internally connected to the encoder section of the  
device. It must be used in conjunction with VF Iand VF I+  
to set the transmit gain for a maximum signal amplitude of  
2.5 V peak. This output can drive a 600 load to 2.5 V peak.  
X
X
VF I–  
X
Voice–Frequency Transmit Input (Inverting)  
This is the inverting input of the transmit gain–adjust  
operational amplifier.  
One bandgap voltage reference generator and digital–to–  
analog converter (DAC) are shared by the transmit and  
receive sections. The autozeroed, switched–capacitor band-  
gap reference generates precise positive and negative refer-  
ence voltages that are independent of temperature and  
power supply voltage. A binary–weighted capacitor array  
(CDAC) forms the chords of the companding structure, while  
a resistor string (RDAC) implements the linear steps within  
each chord. The encode process uses the DAC, the voltage  
reference, and a frame–by–frame autozeroed comparator to  
implement a successive–approximation conversion algo-  
rithm. All of the analog circuitry involved in the data con-  
version — the voltage reference, RDAC, CDAC, and  
comparator — are implemented with a differential architec-  
ture.  
VF I+  
X
Voice–Frequency Transmit Input  
(Non–Inverting)  
This is the non–inverting input of the transmit gain–adjust  
operational amplifier.  
VF O  
R
Voice–Frequency Receive Output  
This receive analog output is capable of driving a 600 Ω  
load to 2.5 V peak.  
VPI  
Voltage Power Input (MC145564/67 Only)  
The receive section includes the DAC described above, a  
sample and hold amplifier, a five–pole 3400 Hz switched  
capacitor low–pass filter with sinX/X correction, and a two–  
pole active smoothing filter to reduce the spectral com-  
ponents of the switched capacitor filter. The output of the  
smoothing filter is a power amplifier that is capable of driving  
a 600 load. The MC145564 and MC145567 add a pair of  
power amplifiers that are connected in a push–pull configu-  
ration; two external resistors set the gain of both of the  
This is the inverting input to the first receive power ampli-  
fier. Both of the receive power amplifiers can be powered  
down by connecting this input to V  
.
BB  
VPO–  
Voltage Power Output (Inverted) (MC145564/67 Only)  
This inverted output of the receive push–pull power ampli-  
fiers can drive 300 to 3.3 V peak.  
MC145554MC145557MC145564MC145567  
MOTOROLA  
4

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