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MC14536BDWR2G PDF预览

MC14536BDWR2G

更新时间： 2024-02-19 19:22:47
品牌 Logo 应用领域
安森美 - ONSEMI 计时器或实时时钟微控制器和处理器外围集成电路光电二极管PC
页数 文件大小 规格书
14页 150K
描述
Programmable Timer

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MC14536BDWR2G 技术参数

是否无铅：不含铅生命周期：Active
零件包装代码：SOIC包装说明：SOP,
针数：16Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
Factory Lead Time：1 week风险等级：0.54
Samacsys Confidence：3Samacsys Status：Released
2D Presentation：https://componentsearchengine.com/2D/0T/225196.1.1.pngSchematic Symbol：https://componentsearchengine.com/symbol.php?partID=225196
PCB Footprint：https://componentsearchengine.com/footprint.php?partID=2251963D View：https://componentsearchengine.com/viewer/3D.php?partID=225196
Samacsys PartID：225196Samacsys Image：https://componentsearchengine.com/Images/9/MC14536BDWR2G.jpg
Samacsys Thumbnail Image：https://componentsearchengine.com/Thumbnails/1/MC14536BDWR2G.jpgSamacsys Pin Count：16
Samacsys Part Category：Integrated CircuitSamacsys Package Category：Small Outline Packages
Samacsys Footprint Name：SOIC-16 WB CASE 751G-03 ISSUE DSamacsys Released Date：2015-08-07 09:42:55
Is Samacsys：N最大时钟频率：2 MHz
JESD-30 代码：R-PDSO-G16JESD-609代码：e3
长度：10.3 mm湿度敏感等级：3
端子数量：16计时器数量：1
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：2.65 mm最大供电电压：18 V
最小供电电压：3 V标称供电电压：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子面层：Tin (Sn)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：40
宽度：7.5 mmuPs/uCs/外围集成电路类型：TIMER, PROGRAMMABLE
Base Number Matches：1

MC14536BDWR2G 数据手册

 浏览型号MC14536BDWR2G的Datasheet PDF文件第2页浏览型号MC14536BDWR2G的Datasheet PDF文件第3页浏览型号MC14536BDWR2G的Datasheet PDF文件第4页浏览型号MC14536BDWR2G的Datasheet PDF文件第6页浏览型号MC14536BDWR2G的Datasheet PDF文件第7页浏览型号MC14536BDWR2G的Datasheet PDF文件第8页 
MC14536B  
PIN DESCRIPTIONS  
INPUTS  
OSC INHIBIT (Pin 14) −A high level on this pin stops the  
SET (Pin 1)−A high on Set asynchronously forces Decode  
RC oscillator which allows for very low−power standby  
operation. May also be used, in conjunction with an external  
clock, with essentially the same results as the Clock Inhibit  
input.  
Out to a high level. This is accomplished by setting an output  
conditioning latch to a high level while at the same time  
resetting the 24 flip−flop stages. After Set goes low (inactive),  
the occurrence of the first negative clock transition on IN  
causes Decode Out to go low. The counter’s flip−flop stages  
MONO−IN (Pin 15) − Used as the timing pin for the  
on−chip monostable multivibrator. If the Mono−In input is  
1
begin counting on the second negative clock transition of IN .  
connected to V , the monostable circuit is disabled, and  
1
SS  
When Set is high, the on−chip RC oscillator is disabled. This  
allows for very low−power standby operation.  
Decode Out is directly connected to the selected Q output.  
The monostable circuit is enabled if a resistor is connected  
RESET (Pin 2) − A high on Reset asynchronously forces  
Decode Out to a low level; all 24 flip−flop stages are also reset  
to a low level. Like the Set input, Reset disables the on−chip  
RC oscillator for standby operation.  
between Mono−In and V . This resistor and the device’s  
internal capacitance will determine the minimum output  
pulse widths. With the addition of an external capacitor to  
DD  
V , the pulse width range may be extended. For reliable  
SS  
IN (Pin 3) −The device’s internal counters advance on the  
operation the resistor value should be limited to the range of  
5 kW to 100 kW and the capacitor value should be limited to  
a maximum of 1000 pf. (See figures 5, 6, 7, and 12).  
A, B, C, D (Pins 9, 10, 11, 12) − These inputs select the  
flip−flop stage to be connected to Decode Out. (See the truth  
tables.)  
1
negative−going edge of this input. IN may be used as an  
1
external clock input or used in conjunction with OUT and  
1
OUT to form an RC oscillator. When an external clock is  
2
used, both OUT and OUT may be left unconnected or used  
1
2
to drive 1 LSTTL or several CMOS loads.  
8−BYPASS (Pin 6) −A high on this input causes the first 8  
flip−flop stages to be bypassed. This device essentially  
becomes a 16−stage counter with all 16 stages selectable.  
Selection is accomplished by the A, B, C, and D inputs. (See  
the truth tables.)  
CLOCK INHIBIT (Pin 7) − A high on this input  
disconnects the first counter stage from the clocking source.  
This holds the present count and inhibits further counting.  
However, the clocking source may continue to run.  
Therefore, when Clock Inhibit is brought low, no oscillator  
startup time is required. When Clock Inhibit is low, the  
counter will start counting on the occurrence of the first  
OUTPUTS  
OUT , OUT (Pin 4, 5) −Outputs used in conjunction with  
1
2
IN to form an RC oscillator. These outputs are buffered and  
1
0
may be used for 2 frequency division of an external clock.  
DECODE OUT (Pin 13) − Output function depends on  
configuration. When the monostable circuit is disabled, this  
output is a 50% duty cycle square wave during free run.  
TEST MODE  
The test mode configuration divides the 24 flip−flop  
stages into three 8−stage sections to facilitate a fast test  
sequence. The test mode is enabled when 8−Bypass, Set and  
Reset are at a high level. (See Figure 10.)  
negative edge of the clocking source at IN .  
1
TRUTH TABLES  
Input  
Input  
Stage Selected  
for Decode Out  
Stage Selected  
for Decode Out  
8−Bypass  
D
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
C
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
8−Bypass  
D
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
C
B
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
9
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
2
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
http://onsemi.com  
5
12345678...14

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