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MC14536BCPS

更新时间： 2024-01-11 07:24:30

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		/
页数	文件大小	规格书
13页	333K
描述
Analog Waveform Generation Function, CMOS, PDIP16

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技术参数
数据手册

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MC14536BCPS 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	SOIC
包装说明：	SOP,	针数：	16
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.6	计数方向：	UP
系列：	4000/14000/40000	JESD-30 代码：	R-PDSO-G16
JESD-609代码：	e4	长度：	10.2 mm
负载/预设输入：	YES	逻辑集成电路类型：	BINARY COUNTER
工作模式：	SYNCHRONOUS	湿度敏感等级：	3
位数：	4	功能数量：	1
端子数量：	16	最高工作温度：	125 °C
最低工作温度：	-55 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	峰值回流温度（摄氏度）：	260
传播延迟（tpd）：	14000 ns	认证状态：	Not Qualified
座面最大高度：	2.05 mm	最大供电电压 (Vsup)：	18 V
最小供电电压 (Vsup)：	3 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	温度等级：	MILITARY
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	40	触发器类型：	POSITIVE EDGE
宽度：	5.275 mm	最小 fmax：	2 MHz
Base Number Matches：	1

MC14536BCPS 数据手册

PIN DESCRIPTIONS

INPUTS

SET (Pin 1) — A high on Set asynchronously forces

Decode Out to a high level. This is accomplished by setting

an output conditioning latch to a high level while at the same

time resetting the 24 flip–flop stages. After Set goes low

(inactive), the occurrence of the first negative clock transition

OSC INHIBIT (Pin 14) — A high level on this pin stops the

RC oscillator which allows for very low–power standby op-

eration. May also be used, in conjunction with an external

clock, with essentially the same results as the Clock Inhibit

input.

MONO–IN (Pin 15) — Used as the timing pin for the on–

chip monostable multivibrator. If the Mono–In input is con-

on IN causes Decode Out to go low. The counter’s flip–flop

stages begin counting on the second negative clock transi-

nected to V

, the monostable circuit is disabled, and

Decode Out is directly connected to the selected Q output.

The monostable circuit is enabled if a resistor is connected

between Mono–In and V

ternal capacitance will determine the minimum output pulse

widths. With the addition of an external capacitor to V , the

pulse width range may be extended. For reliable operation

the resistor value should be limited to the range of 5 kΩ to

100 kΩ and the capacitor value should be limited to a maxi-

mum of 1000 pf. (See figures 3, 4, 5, and 10).

A, B, C, D (Pins 9, 10, 11, 12) — These inputs select the

flip–flop stage to be connected to Decode Out. (See the truth

tables.)

tion of IN . When Set is high, the on–chip RC oscillator is

disabled. This allows for very low–power standby operation.

RESET (Pin 2) — A high on Reset asynchronously forces

Decode Out to a low level; all 24 flip–flop stages are also

reset to a low level. Like the Set input, Reset disables the

on–chip RC oscillator for standby operation.

. This resistor and the device’s in-

IN (Pin 3) — The device’s internal counters advance on

the negative–going edge of this input. IN may be used as an

external clock input or used in conjunction with OUT and

OUT to form an RC oscillator. When an external clock is

used, both OUT and OUT may be left unconnected or

used to drive 1 LSTTL or several CMOS loads.

OUTPUTS

8–BYPASS (Pin 6) — A high on this input causes the first

8 flip–flop stages to be bypassed. This device essentially be-

comes a 16–stage counter with all 16 stages selectable.

Selection is accomplished by the A, B, C, and D inputs. (See

the truth tables.)

CLOCK INHIBIT (Pin 7) — A high on this input discon-

nects the first counter stage from the clocking source. This

holds the present count and inhibits further counting. How-

ever, the clocking source may continue to run. Therefore,

when Clock Inhibit is brought low, no oscillator start–up time

is required. When Clock Inhibit is low, the counter will start

counting on the occurrence of the first negative edge of the

OUT , OUT (Pin 4, 5) — Outputs used in conjunction with

IN to form an RC oscillator. These outputs are buffered and

may be used for 2 frequency division of an external clock.

DECODE OUT (Pin 13) — Output function depends on

configuration. When the monostable circuit is disabled, this

output is a 50% duty cycle square wave during free run.

TEST MODE

The test mode configuration divides the 24 flip–flop stages

into three 8–stage sections to facilitate a fast test sequence.

The test mode is enabled when 8–Bypass, Set and Reset

are at a high level. (See Figure 8.)

clocking source at IN .

MC14536B

MOTOROLA CMOS LOGIC DATA

1 2 345 6 7...13

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