Order this document
by MC141541/D
SEMICONDUCTOR TECHNICAL DATA
P SUFFIX
PLASTIC DIP
CASE 648
CMOS
The MC141541 is a high performance HCMOS device designed to interface
with a microcontroller unit to allow colored symbols or characters to be
displayed on a color monitor. The on–chip PLL allows both multi–system
operation and self–generation of system timing. It also minimizes the MCU’s
burden through its built–in 273 bytes display/control RAM. By storing a full
screen of data and control information, this device has the capability to carry out
‘screen–refresh’ without MCU supervision.
Since there is no spacing between characters, special graphics–oriented
characters can be generated by combining two or more character blocks. There
are two different resolutions that users can choose. By changing the number of
dots per horizontal line to 320 (CGA) or 480 (EGA), smaller characters with
higher resolution can be easily achieved.
Special functions such as character bordering or shadowing, multi–level
windows, double height and double width, and programmable vertical length of
character can also be incorporated. Furthermore, neither massive information
update nor extremely high data transmission rate are expected for normal on–
screen display operation, and serial protocols are implemented in lieu of any
parallel formats to achieve minimum pin count.
A special feature, character RAM fonts, is implemented in this MOSD
enhanced version (EMOSD). Users can download their own fonts and display
them at any time once the chip is powered on. There are two ways for users to
build and store fonts. One is a conventional approach to have masked ROM
fonts. A newer approach is to store the fonts in the EPROM accessed by the
MCU and then download them into the EMOSD character RAM. With this new
technique, users have more flexibility in preparing their fonts and the effective
number of fonts is greatly increased.
ORDERING INFORMATION
MC141541P
Plastic DIP
PIN ASSIGNMENT
V
V
1
2
16
15
V
SS(A)
SS
VCO
R
RP
)
3
4
5
6
7
8
14
13
12
11
10
9
G
B
DD(A
HFLB
FBKG
HTONE/
PWMCK
SS
VFLB
SDA(MOSI)
SCL(SCK)
V
DD
•
•
•
•
•
Two Selectable Resolutions: 320 (CGA) and 480 (EGA) Dots per Line
Fully Programmable Character Array of 10 Rows by 24 Columns
273 Bytes Direct Mapping Display RAM Architecture
Internal PLL Generates a Wide–Ranged System Clock
For High–End Monitor Application, Maximum Horizontal Frequency is
110 kHz (52.8 MHz Dot Clock at 480 Mode)
Programmable Vertical Height of Character to Meet Multi–Sync
Requirement
•
•
•
Programmable Vertical and Horizontal Positioning for Display Center
120 Characters and Graphic Symbols ROM and Eight Programmable
Character RAM
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•
•
•
•
•
10 x 16 Dot Matrix Character
Character–by–Character Color Selection
A Maximum of Four Selectable Colors per Row
Double Character Height and Double Character Width
Character Bordering or Shadowing
Three Fully Programmable Background Windows with Overlapping
Capability
•
Provides a Clock Output Synchronous to the Incoming H Sync for External
PWM
•
•
M_BUS (IIC) Interface with Address $7A
Single Positive 5 V Supply
REV 1
2/97
TN97031200
Motorola, Inc. 1997
MOTOROLA
MC141541
1