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MC14081BCPG PDF预览

MC14081BCPG

更新时间： 2024-11-04 20:28:03
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 栅光电二极管逻辑集成电路触发器
页数 文件大小 规格书
12页 158K
描述
AND Gate, 4000/14000/40000 Series, 4-Func, 2-Input, CMOS, PDIP14, ROHS COMPLIANT, PLASTIC, DIP-14

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MC14081BCPG 技术参数

生命周期：Contact Manufacturer包装说明：ROHS COMPLIANT, PLASTIC, DIP-14
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.6Is Samacsys：N
系列：4000/14000/40000JESD-30 代码：R-PDIP-T14
长度：18.86 mm逻辑集成电路类型：AND GATE
功能数量：4输入次数：2
端子数量：14最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装形状：RECTANGULAR
封装形式：IN-LINE传播延迟（tpd）：300 ns
座面最大高度：4.69 mm最大供电电压 (Vsup)：18 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：CMOS
温度等级：MILITARY端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
宽度：7.62 mmBase Number Matches：1

MC14081BCPG 数据手册

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MC14001B Series  
B-Suffix Series CMOS Gates  
MC14001B, MC14011B, MC14023B,  
MC14025B, MC14071B, MC14073B,  
MC14081B, MC14082B  
The B Series logic gates are constructed with P and N channel  
enhancement mode devices in a single monolithic structure  
(Complementary MOS). Their primary use is where low power  
dissipation and/or high noise immunity is desired.  
http://onsemi.com  
MARKING  
Features  
DIAGRAMS  
• Supply Voltage Range = 3.0 Vdc to 18 Vdc  
14  
PDIP−14  
P SUFFIX  
CASE 646  
• All Outputs Buffered  
MC140xxBCP  
AWLYYWWG  
• Capable of Driving Two Low−power TTL Loads or One Low−power  
Schottky TTL Load Over the Rated Temperature Range.  
• Double Diode Protection on All Inputs Except: Triple Diode  
Protection on MC14011B and MC14081B  
• Pin−for−Pin Replacements for Corresponding CD4000 Series  
B Suffix Devices  
1
14  
SOIC−14  
D SUFFIX  
CASE 751A  
140xxBG  
AWLYWW  
1
• These Devices are Pb−Free and are RoHS Compliant  
14  
• NLV Prefix for Automotive and Other Applications Requiring  
Unique Site and Control Change Requirements; AEC−Q100  
Qualified and PPAP Capable  
14  
0xxB  
ALYWG  
G
TSSOP−14  
DT SUFFIX  
CASE 948G  
MAXIMUM RATINGS (Voltages Referenced to V  
)
SS  
1
Symbol  
Parameter  
Value  
−0.5 to +18.0  
Unit  
V
xx  
A
WL, L  
YY, Y  
= Specific Device Code  
= Assembly Location  
= Wafer Lot  
V
DD  
DC Supply Voltage Range  
V , V  
in out  
Input or Output Voltage Range  
(DC or Transient)  
−0.5 to V + 0.5  
V
DD  
= Year  
WW, W = Work Week  
I , I  
in out  
Input or Output Current  
(DC or Transient) per Pin  
10  
mA  
G or G  
= Pb−Free Package  
(Note: Microdot may be in either location)  
P
D
Power Dissipation, per Package  
(Note 1)  
500  
mW  
DEVICE INFORMATION  
T
Ambient Temperature Range  
Storage Temperature Range  
−55 to +125  
−65 to +150  
260  
°C  
°C  
°C  
A
Device  
MC14001B  
MC14011B  
Description  
T
stg  
Quad 2−Input NOR Gate  
Quad 2−Input NAND Gate  
T
Lead Temperature  
(8−Second Soldering)  
L
V
ESD Withstand Voltage  
Human Body Model  
Machine Model  
V
MC14023B  
MC14025B  
MC14071B  
MC14073B  
Triple 3−Input NAND Gate  
Triple 3−Input NOR Gate  
Quad 2−Input OR Gate  
Triple 3−Input AND Gate  
ESD  
> 3000  
> 300  
N/A  
Charged Device Model  
Stresses exceeding Maximum Ratings may damage the device. Maximum  
Ratings are stress ratings only. Functional operation above the Recommended  
Operating Conditions is not implied. Extended exposure to stresses above the  
Recommended Operating Conditions may affect device reliability.  
1. Temperature Derating:  
MC14081B  
MC14082B  
Quad 2−Input AND Gate  
Dual 4−Input AND Gate  
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C  
This device contains protection circuitry to guard against damage due to high  
static voltages or electric fields. However, precautions must be taken to avoid  
applications of any voltage higher than maximum rated voltages to this  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 8 of this data sheet.  
high−impedance circuit. For proper operation, V and V should be constrained  
in  
out  
to the range V v (V or V ) v V  
.
SS  
in  
out  
DD  
Unused inputs must always be tied to an appropriate logic voltage level  
(e.g., either V or V ). Unused outputs must be left open.  
SS  
DD  
© Semiconductor Components Industries, LLC, 2013  
1
Publication Order Number:  
April, 2013 − Rev. 10  
MC14001B/D  
 
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