MC14029B
Binary/Decade Up/Down
Counter
The MC14029B Binary/Decade up/down counter is constructed
with MOS P−channel and N−channel enhancement mode devices in a
single monolithic structure. The counter consists of type D flip−flop
stages with a gating structure to provide toggle flip−flop capability.
The counter can be used in either Binary or BCD operation. This
complementary MOS counter finds primary use in up/down and
difference counting and frequency synthesizer applications where low
power dissipation and/or high noise immunity is desired. It is also
useful in A/D and D/A conversion and for magnitude and sign
generation.
http://onsemi.com
MARKING
DIAGRAMS
16
PDIP−16
MC14029BCP
AWLYYWWG
P SUFFIX
CASE 648
1
Features
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Internally Synchronous for High Speed
• Logic Edge−Clocked Design − Count Occurs on Positive Going Edge
of Clock
16
SOIC−16
D SUFFIX
14029BG
AWLYWW
CASE 751B
1
16
• Asynchronous Preset Enable Operation
SOEIAJ−16
F SUFFIX
CASE 966
• Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
• Pin for Pin Replacement for CD4029B
MC14029B
ALYWG
1
• Pb−Free Packages are Available*
A
= Assembly Location
WL, L
YY, Y
= Wafer Lot
= Year
MAXIMUM RATINGS (Voltages Referenced to V
)
SS
Symbol
Parameter
Value
−0.5 to +18.0
Unit
V
WW, W = Work Week
= Pb−Free Indicator
V
DC Supply Voltage Range
G
DD
V , V
in out
Input or Output Voltage Range
(DC or Transient)
−0.5 to V + 0.5
V
DD
PIN ASSIGNMENT
I , I
Input or Output Current
(DC or Transient) per Pin
10
mA
in out
PE
1
2
3
4
5
6
7
8
16
V
DD
Q3
P3
P0
15 CLK
14 Q2
13 P2
12 P1
11 Q1
10 U/D
P
T
Power Dissipation, per Package
(Note 1)
500
mW
D
Ambient Temperature Range
Storage Temperature Range
−55 to +125
−65 to +150
260
°C
°C
°C
A
T
stg
C
in
T
Lead Temperature
(8−Second Soldering)
L
Q0
C
out
SS
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
V
9
B/D
1. Temperature Derating:
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V and V should be constrained
in
out
*For additional information on our Pb−Free strategy
and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
to the range V v (V or V ) v V
.
DD
SS
in
out
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V or V ). Unused outputs must be left open.
SS
DD
©
Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
August, 2005 − Rev. 6
MC14029B/D