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MC100EL29DW

更新时间： 2024-11-24 04:16:59
品牌 Logo 应用领域
安森美 - ONSEMI 触发器逻辑集成电路光电二极管时钟
页数 文件大小 规格书
6页 116K
描述
5V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset

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中文翻译

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MC100EL29DW 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：SOIC包装说明：SOIC-20
针数：20Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.44
其他特性：NECL MODE: VCC = 0V WITH VEE = -4.2V TO -5.7V系列：100EL
JESD-30 代码：R-PDSO-G20JESD-609代码：e0
长度：12.8 mm逻辑集成电路类型：D FLIP-FLOP
位数：1功能数量：2
端子数量：20最高工作温度：85 °C
最低工作温度：-40 °C输出特性：OPEN-EMITTER
输出极性：COMPLEMENTARY封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP20,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：240电源：-4.5 V
传播延迟（tpd）：0.7 ns认证状态：Not Qualified
座面最大高度：2.65 mm子类别：FF/Latches
最大供电电压 (Vsup)：5.7 V最小供电电压 (Vsup)：4.2 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：ECL温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn80Pb20)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30触发器类型：POSITIVE EDGE
宽度：7.5 mm最小 fmax：1100 MHz
Base Number Matches：1

MC100EL29DW 数据手册

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MC100EL29  
5VꢀECL Dual Differential  
Data and Clock D Flip−Flop  
With Set and Reset  
Description  
http://onsemi.com  
The MC100EL29 is a dual master−slave flip flop. The device  
features fully differential Data and Clock inputs as well as outputs.  
Data enters the master latch when the clock is LOW and transfers to  
the slave upon a positive transition on the clock input.  
The V pin, an internally generated voltage supply, is available to  
BB  
this device only. For single-ended input conditions, the unused  
SO−20  
WB SUFFIX  
CASE 751D  
differential input is connected to V as a switching reference voltage.  
BB  
V
BB  
may also rebias AC coupled inputs. When used, decouple V  
BB  
and V via a 0.01 mF capacitor and limit current sourcing or sinking  
CC  
to 0.5 mA. When not used, V should be left open.  
BB  
The differential inputs have special circuitry which ensures device  
stability under open input conditions. When both differential inputs  
are left open the D input will pull down to V and the D input will  
MARKING DIAGRAM*  
EE  
bias around V /2. The outputs will go to a defined state, however the  
CC  
state will be random based on how the flip flop powers up.  
Both flip flops feature asynchronous, overriding Set and Reset  
inputs. Note that the Set and Reset inputs cannot both be HIGH  
simultaneously.  
20  
100EL29  
AWLYYWWG  
The 100 Series Contains Temperature Compensation  
Features  
1
• 1100 MHz Flip−Flop Toggle Frequency  
• 580 ps Propagation Delays  
A
= Assembly Location  
= Wafer Lot  
= Year  
= Work Week  
= Pb−Free Package  
WL  
YY  
WW  
G
• Q Output will Default LOW with Inputs Open or at V  
EE  
• PECL Mode Operating Range: V = 4.2 V to 5.7 V  
CC  
with V = 0 V  
EE  
• NECL Mode Operating Range: V = 0 V  
CC  
*For additional marking information, refer to  
Application Note AND8002/D.  
with V = −4.2 V to −5.7 V  
EE  
• Internal Input Pulldown Resistors on D(s), CLK(s), S(s), and R(s).  
• ESD Protection: Human Body Model; > 2 kV,  
Machine Model; > 100 V  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 5 of this data sheet.  
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test  
• Moisture Sensitivity Level:  
Pb = 1  
Pb−Free = 3  
For Additional Information, see Application Note AND8003/D  
• Flammability Rating: UL 94 V−0 @ 1.125 in,  
Oxygen Index: 28 to 34  
• Transistor Count = 313 devices  
• Pb−Free Package is Available*  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
October, 2006 − Rev. 4  
MC100EL29/D  
123456

中文翻译

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MC100EL29DW 替代型号

型号 品牌 替代类型 描述 数据表
MC100EL29DWG ONSEMI

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