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MC100EL11DR2 PDF预览

MC100EL11DR2

更新时间: 2024-02-10 22:57:26
品牌 Logo 应用领域
安森美 - ONSEMI 逻辑集成电路光电二极管输出元件驱动
页数 文件大小 规格书
9页 151K
描述
5.0 V ECL 1:2 Differential Fanout Buffer

MC100EL11DR2 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP, SOP8,.25针数:8
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:5.15
其他特性:NECL MODE: VCC=0 WITH VEE= -4.2V TO -5.7V系列:100EL
输入调节:DIFFERENTIALJESD-30 代码:R-PDSO-G8
JESD-609代码:e3长度:4.9 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER湿度敏感等级:1
功能数量:1反相输出次数:
端子数量:8实输出次数:2
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:OPEN-EMITTER封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:-4.5 V
Prop。Delay @ Nom-Sup:0.37 ns传播延迟(tpd):0.34 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.02 ns
座面最大高度:1.75 mm子类别:Clock Drivers
最大供电电压 (Vsup):5.7 V最小供电电压 (Vsup):4.2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:ECL温度等级:INDUSTRIAL
端子面层:Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:3.9 mm
Base Number Matches:1

MC100EL11DR2 数据手册

 浏览型号MC100EL11DR2的Datasheet PDF文件第2页浏览型号MC100EL11DR2的Datasheet PDF文件第3页浏览型号MC100EL11DR2的Datasheet PDF文件第4页浏览型号MC100EL11DR2的Datasheet PDF文件第5页浏览型号MC100EL11DR2的Datasheet PDF文件第6页浏览型号MC100EL11DR2的Datasheet PDF文件第7页 
MC10EL11, MC100EL11  
5.0 VꢀECL 1:2 Differential  
Fanout Buffer  
The MC10EL/100EL11 is a differential 1:2 fanout buffer. The device  
is functionally similar to the E111 device but with higher performance  
capabilities. The within-device skew and propagation delay is  
significantly improved over the E111.  
http://onsemi.com  
The differential inputs of the EL11 employ clamping circuitry to  
maintain stability under open input conditions. If the inputs are left open  
MARKING  
DIAGRAMS*  
(pulled to V ) the Q outputs will go LOW.  
EE  
The 100 Series contains temperature compensation.  
8
1
8
8
Features  
265 ps Propagation Delay  
5 ps Skew Between Outputs  
HEL11  
ALYW  
KEL11  
ALYW  
G
1
G
SOIC8  
D SUFFIX  
CASE 751  
1
PECL Mode Operating Range: V = 4.2 V to 5.7 with V = 0 V  
CC  
EE  
NECL Mode Operating Range: V = 0 V with V = 4.2 V to 5.7 V  
Internal Input Pulldown Resistors  
PbFree Packages are Available  
CC  
EE  
8
1
8
8
HL11  
ALYWG  
G
KL11  
ALYWG  
G
1
TSSOP8  
DT SUFFIX  
CASE 948R  
1
Q
Q
1
2
8
7
V
CC  
0
0
D
D
1
4
1
4
DFN8  
MN SUFFIX  
CASE 506AA  
Q
Q
3
4
6
5
1
1
H = MC10  
= MC100  
4Q= MC10  
L = Wafer Lot  
Y = Year  
W = Work Week  
M = Date Code  
K
V
EE  
2E = MC100  
A
= Assembly Location  
G
= PbFree Package  
(Note: Microdot may be in either location)  
*For additional marking information, refer to  
Application Note AND8002/D.  
Figure 1. Logic Diagram and Pinout Assignment  
Table 1. PIN DESCRIPTION  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 6 of this data sheet.  
PIN  
FUNCTION  
D, D  
ECL Data Inputs  
Q0, Q0; Q1, Q1  
ECL Data Outputs  
VCC  
VEE  
EP  
Positive Supply  
Negative Supply  
Exposed pad must be connected to a  
sufficient thermal conduit. Electrically  
connect to the most negative supply or  
leave floating open.  
© Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
December, 2006Rev. 9  
MC10EL11/D  

MC100EL11DR2 替代型号

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MC10EL11DR2G ONSEMI

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