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MC100EL05MNR4 PDF预览

MC100EL05MNR4

更新时间: 2024-11-20 05:22:27
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
9页 153K
描述
5V ECL 2-Input Differential AND/NAND

MC100EL05MNR4 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:DFN
包装说明:HVSSON, SOLCC8,.08,20针数:8
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.48其他特性:NECL MODE: VCC = 0V WITH VEE = -4.2V TO -5.7V
系列:100ELJESD-30 代码:S-XDSO-N8
JESD-609代码:e0长度:2 mm
逻辑集成电路类型:AND/NAND GATE功能数量:1
输入次数:2端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:HVSSON
封装等效代码:SOLCC8,.08,20封装形状:SQUARE
封装形式:SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
峰值回流温度(摄氏度):240电源:-4.5 V
最大电源电流(ICC):25 mAProp。Delay @ Nom-Sup:0.44 ns
传播延迟(tpd):0.39 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:1 mm
子类别:Gates最大供电电压 (Vsup):5.7 V
最小供电电压 (Vsup):4.2 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:ECL
温度等级:INDUSTRIAL端子面层:TIN LEAD
端子形式:NO LEAD端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:2 mmBase Number Matches:1

MC100EL05MNR4 数据手册

 浏览型号MC100EL05MNR4的Datasheet PDF文件第2页浏览型号MC100EL05MNR4的Datasheet PDF文件第3页浏览型号MC100EL05MNR4的Datasheet PDF文件第4页浏览型号MC100EL05MNR4的Datasheet PDF文件第5页浏览型号MC100EL05MNR4的Datasheet PDF文件第6页浏览型号MC100EL05MNR4的Datasheet PDF文件第7页 
MC10EL05, MC100EL05  
5VꢀECL 2-Input Differential  
AND/NAND  
The MC10EL/100EL05 is a 2-input differential AND/NAND gate.  
The device is functionally equivalent to the E404 device with higher  
performance capabilities. With propagation delays and output transition  
times significantly faster than the E404, the EL05 is ideally suited for  
those applications which require the ultimate in AC performance.  
Because a negative 2-input NAND is equivalent to a 2-input OR  
function, the differential inputs and outputs of the device allows the EL05  
to also be used as a 2-input differential OR/NOR gate.  
http://onsemi.com  
MARKING  
DIAGRAMS*  
8
The differential inputs employ clamp circuitry so that under open input  
8
1
8
1
conditions (pulled down to V ) the input to the AND gate will be  
EE  
HEL05  
ALYW  
G
KEL05  
ALYW  
G
HIGH. In this way, if one set of inputs is open, the gate will remain active  
SOIC8  
D SUFFIX  
CASE 751  
to the other input.  
The 100 Series contains temperature compensation.  
1
8
Features  
8
8
1
275 ps Propagation Delay  
1
HL05  
ALYWG  
G
KL05  
ESD Protection: > 1 kV Human Body Model,  
TSSOP8  
DT SUFFIX  
CASE 948R  
ALYWG  
> 100 V Machine Model  
G
PECL Mode Operating Range: V = 4.2 V to 5.7 V with V = 0 V  
CC  
EE  
1
NECL Mode Operating Range: V = 0 V with V = 4.2 V to 5.7 V  
CC  
EE  
Internal Input Pulldown Resistors  
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test  
Moisture Sensitivity Level 1  
DFN8  
MN SUFFIX  
CASE 506AA  
For Additional Information, see Application Note AND8003/D  
1
4
1
4
Flammability Rating: UL 94 V0 @ 0.125 in,  
Oxygen Index: 28 to 34  
Transistor Count = 44 devices  
PbFree Packages are Available  
L
= Wafer Lot  
= Year  
= Work Week  
= Date Code  
= PbFree Package  
H
K
= MC10  
= MC100  
Y
W
D
G
4O = MC10  
2C = MC100  
A
= Assembly Location  
(Note: Microdot may be in either location)  
*For additional marking information, refer to  
Application Note AND8002/D.  
D
D
1
2
8
7
V
CC  
0
0
Q
Q
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 6 of this data sheet.  
D
D
3
4
6
5
1
1
V
EE  
Figure 1. Logic Diagram and Pinout  
Assignment  
© Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
December, 2006 Rev. 5  
MC10EL05/D  

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