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MBM29LV800TA-70PBT PDF预览

MBM29LV800TA-70PBT

更新时间： 2024-02-19 13:10:23
品牌 Logo 应用领域
飞索 - SPANSION 内存集成电路
页数 文件大小 规格书
53页 587K
描述
Flash, 512KX16, 70ns, PBGA48, PLASTIC, FBGA-48

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MBM29LV800TA-70PBT 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：PLASTIC, FBGA-48
针数：48Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.32.00.51
风险等级：5.21最长访问时间：70 ns
其他特性：MINIMUM 100000 PROGRAM/ERASE CYCLES备用内存宽度：8
启动块：TOPJESD-30 代码：R-PBGA-B48
JESD-609代码：e0长度：9 mm
内存密度：8388608 bit内存集成电路类型：FLASH
内存宽度：16功能数量：1
端子数量：48字数：524288 words
字数代码：512000工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：512KX16封装主体材料：PLASTIC/EPOXY
封装代码：TFBGA封装形状：RECTANGULAR
封装形式：GRID ARRAY, THIN PROFILE, FINE PITCH并行/串行：PARALLEL
峰值回流温度（摄氏度）：240编程电压：3 V
认证状态：Not Qualified座面最大高度：1.2 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：TIN LEAD端子形式：BALL
端子节距：0.8 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：30类型：NOR TYPE
宽度：6 mmBase Number Matches：1

MBM29LV800TA-70PBT 数据手册

 浏览型号MBM29LV800TA-70PBT的Datasheet PDF文件第2页浏览型号MBM29LV800TA-70PBT的Datasheet PDF文件第3页浏览型号MBM29LV800TA-70PBT的Datasheet PDF文件第4页浏览型号MBM29LV800TA-70PBT的Datasheet PDF文件第5页浏览型号MBM29LV800TA-70PBT的Datasheet PDF文件第6页浏览型号MBM29LV800TA-70PBT的Datasheet PDF文件第7页 
FUJITSU SEMICONDUCTOR  
DATA SHEET  
DS05-20845-5E  
FLASH MEMORY  
CMOS  
8M (1M × 8/512K × 16) BIT  
MBM29LV800TA-70/-90/MBM29LV800BA-70/-90  
■ DESCRIPTION  
The MBM29LV800TA/BA are a 8M-bit, 3.0 V-only Flash memory organized as 1M bytes of 8 bits each or 512K  
words of 16 bits each. The MBM29LV800TA/BA are offered in a 48-pin TSOP(I), 44-pin SOP, and 48-ball FBGA  
packages. These devices are designed to be programmed in-system with the standard system 3.0 V VCC supply.  
12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also be reprogrammed  
in standard EPROM programmers.  
The standard MBM29LV800TA/BA offer access times 70 ns and 90 ns, allowing operation of high-speed  
microprocessors without wait states. To eliminate bus contention the devices have separate chip enable (CE),  
write enable (WE), and output enable (OE) controls.  
The MBM29LV800TA/BA are pin and command set compatible with JEDEC standard E2PROMs. Commands are  
written to the command register using standard microprocessor write timings. Register contents serve as input  
to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch  
addresses and data needed for the programming and erase operations. Reading data out of the devices is similar  
to reading from 5.0 V and 12.0 V Flash or EPROM devices.  
The MBM29LV800TA/BA are programmed by executing the program command sequence. This will invoke the  
Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths  
and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds.  
Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase  
Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed  
before executing the erase operation. During erase, the devices automatically time the erase pulse widths and  
verify proper cell margin.  
(Continued)  
■ PRODUCT LINE UP  
Part No.  
MBM29LV800TA/MBM29LV800BA  
+0.3 V  
–0.3 V  
VCC = 3.3 V  
VCC = 3.0 V  
-70  
—
—
Ordering Part No.  
+0.6 V  
–0.3 V  
-90  
Max Address Access Time (ns)  
Max CE Access Time (ns)  
Max OE Access Time (ns)  
70  
70  
30  
90  
90  
35  
1234567...53

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MBM29LV800TA-70PF FUJITSU Flash, 512KX16, 70ns, PDSO44, PLASTIC, SOP-44

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MBM29LV800TA-70PF SPANSION Flash, 512KX16, 70ns, PDSO44, PLASTIC, SOP-44

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