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MBM29LV160T-90PBT-SF2-E1 PDF预览

MBM29LV160T-90PBT-SF2-E1

更新时间: 2024-12-01 15:45:23
品牌 Logo 应用领域
飞索 - SPANSION 内存集成电路
页数 文件大小 规格书
60页 768K
描述
Flash, 1MX16, 90ns, PBGA48, PLASTIC, FBGA-48

MBM29LV160T-90PBT-SF2-E1 技术参数

生命周期:Obsolete零件包装代码:BGA
包装说明:PLASTIC, FBGA-48针数:48
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.51风险等级:5.23
最长访问时间:90 ns其他特性:CONFIGURABLE AS 1M X 16
备用内存宽度:8启动块:TOP
JESD-30 代码:R-PBGA-B48长度:9 mm
内存密度:16777216 bit内存集成电路类型:FLASH
内存宽度:16功能数量:1
端子数量:48字数:1048576 words
字数代码:1000000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:1MX16封装主体材料:PLASTIC/EPOXY
封装代码:TFBGA封装形状:RECTANGULAR
封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):240编程电压:3 V
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:BALL端子节距:0.8 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:30
类型:NOR TYPE宽度:8 mm
Base Number Matches:1

MBM29LV160T-90PBT-SF2-E1 数据手册

 浏览型号MBM29LV160T-90PBT-SF2-E1的Datasheet PDF文件第2页浏览型号MBM29LV160T-90PBT-SF2-E1的Datasheet PDF文件第3页浏览型号MBM29LV160T-90PBT-SF2-E1的Datasheet PDF文件第4页浏览型号MBM29LV160T-90PBT-SF2-E1的Datasheet PDF文件第5页浏览型号MBM29LV160T-90PBT-SF2-E1的Datasheet PDF文件第6页浏览型号MBM29LV160T-90PBT-SF2-E1的Datasheet PDF文件第7页 
FUJITSU SEMICONDUCTOR  
DATA SHEET  
DS05-20846-4E  
FLASH MEMORY  
CMOS  
16M (2M × 8/1M × 16) BIT  
-80/-90/-12  
-80/-90/-12  
/MBM29LV160B  
MBM29LV160T  
FEATURES  
• Single 3.0 V read, program and erase  
Minimizes system level power requirements  
• Compatible with JEDEC-standard commands  
Uses same software commands as E2PROMs  
• Compatible with JEDEC-standard world-wide pinouts  
48-pin TSOP (I) (Package suffix: PFTN-Normal Bend Type, PFTR-Reversed Bend Type)  
46-pin SON (Package suffix: PN)  
48-pin CSOP (Package suffix: PCV)  
48-ball FBGA (Package suffix: PBT)  
• Minimum 100,000 program/erase cycles  
• High performance  
80 ns maximum access time  
• Sector erase architecture  
One 8K word, two 4K words, one 16K word, and thirty-one 32K words sectors in word mode  
One 16K byte, two 8K bytes, one 32K byte, and thirty-one 64K bytes sectors in byte mode  
Any combination of sectors can be concurrently erased. Also supports full chip erase  
• Boot Code Sector Architecture  
T = Top sector  
B = Bottom sector  
• Embedded EraseTM Algorithms  
Automatically pre-programs and erases the chip or any sector  
• Embedded programTM Algorithms  
Automatically programs and verifies data at specified address  
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion  
• Ready/Busy output (RY/BY)  
Hardware method for detection of program or erase cycle completion  
• Automatic sleep mode  
When addresses remain stable, automatically switches themselves to low power mode  
• Low VCC write inhibit 2.5 V  
(Continued)  
Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.  

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