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MB96F385YWAPMC-GSE2 PDF预览

MB96F385YWAPMC-GSE2

更新时间: 2024-11-19 00:53:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 微控制器
页数 文件大小 规格书
117页 9867K
描述
F2MC-16FX 16-bit Proprietary Microcontroller

MB96F385YWAPMC-GSE2 数据手册

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MB96380 Series  
F2MC-16FX 16-bit Proprietary  
Microcontroller  
MB96380 series is based on Cypress advanced 16FX architecture (16-bit with instruction pipeline for RISC-like performance).  
The CPU uses the same instruction set as the established 16LX series - thus allowing for easy migration of 16LX Software to the  
new 16FX products. 16FX improvements compared to the previous generation include significantly improved performance - even  
at the same operation frequency, reduced power consumption and faster start-up time.  
For highest processing speed at optimized power consumption an internal PLL can be selected to supply the CPU with up to  
56MHz operation frequency from an external 4MHz resonator. The result is a minimum instruction cycle time of 17.8ns going  
together with excellent EMI behavior. An on-chip clock modulation circuit significantly reduces emission peaks in the frequency  
spectrum. The emitted power is minimized by the on-chip voltage regulator that reduces the internal CPU voltage. A flexible clock  
tree allows to select suitable operation frequencies for peripheral resources independent of the CPU speed.  
Note: MB96384/385/F385/F388/F389 devices are under development and specification is preliminary. These products under  
development may change its specification without notice.  
Features  
Technology  
On-chip voltage regulator  
0.18m CMOS  
Internal voltage regulator supports reduced internal MCU  
voltage, offering low EMI and low power consumption figures  
CPU  
F2MC-16FX CPU  
Low voltage reset  
Reset is generated when supply voltage is below minimum.  
Up to 56 MHz internal, 17.8 ns instruction cycle time  
Code Security  
Optimized instruction set for controller applications (bit, byte,  
word and long-word data types; 23 different addressing  
modes; barrel shift; variety of pointers)  
Protects ROM content from unintended read-out  
Memory Patch Function  
8-byte instruction execution queue  
Replaces ROM content  
Signed multiply (16-bit  16-bit) and divide (32-bit/16-bit)  
instructions available  
Can also be used to implement embedded debug support  
System clock  
DMA  
On-chip PLL clock multiplier (x1 - x25, x1 when PLL stop)  
Automatic transfer function independent of CPU, can be  
assigned freely to resources  
3 MHz - 16 MHz external crystal oscillator clock (maximum  
frequency when using ceramic resonator depends on  
Q-factor).  
Interrupts  
Fast Interrupt processing  
8 programmable priority levels  
Non-Maskable Interrupt (NMI)  
Up to 56 MHz external clock for devices with fast clock input  
feature  
32-100 kHz subsystem quartz clock  
100kHz/2MHz internal RC clock for quick and safe startup,  
oscillator stop detection, watchdog  
Timers  
Three independent clock timers (23-bit RC clock timer, 23-bit  
Main clock timer, 17-bit Sub clock timer)  
Clock source selectable from main- and subclock oscillator  
(part number suffix “W”) and on-chip RC oscillator,  
independently for CPU and 2 clock domains of peripherals.  
Watchdog Timer  
Low Power Consumption - 13 operating modes : (different  
Run, Sleep, Timer modes, Stop mode)  
Clock modulator  
Cypress Semiconductor Corporation  
Document Number: 002-04582 Rev. *A  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised April 28, 2016  

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