MB95690K Series
New 8FX 8-bit Microcontrollers
The MB95690K Series is a series of general-purpose, single-chip microcontrollers. In addition to a compact instruction set, the
microcontrollers of this series contain a variety of peripheral functions.
❐ Waveform sequencer (including a 16-bit timer equipped with
Features
a buffer and a compare clear function)
■ F2MC-8FX CPU core
■ LIN-UART
❐ Instruction set optimized for controllers
❐ Full duplex double buffer
• Multiplication and division instructions
❐ Capableofclockasynchronousserialdatatransferandclock
synchronous serial data transfer
• 16-bit arithmetic operations
• Bit test branch instructions
• Bit manipulation instructions, etc.
■ External interrupt
❐ LQF044: 7 channels
❐ LQA048, LQC052, WNR048: 8 channels
❐ Interrupt by edge detection (rising edge, falling edge, and
both edges can be selected)
❐ Can be used to wake up the device from different low power
consumption (standby) modes
■ Clock
❐ Selectable main clock source
• Main oscillation clock (up to 16.25 MHz, maximum ma-
chine clock frequency: 8.125 MHz)
• External clock (up to 32.5 MHz, maximum machine clock
frequency: 16.25 MHz)
■ 8/10-bit A/D converter
❐ LQF044: 8 channels
• Main CR clock (4 MHz 2%)
❐ LQA048, LQC052, WNR048: 12 channels
❐ 8-bit or 10-bit resolution can be selected.
• Main CR PLL clock
- The main CR PLL clock frequency becomes 8 MHz
2% when the PLL multiplication rate is 2.
■ Low power consumption (standby) modes
❐ There are four standby modes as follows:
• Stop mode
• Sleep mode
• Watch mode
• Time-base timer mode
❐ Instandbymode, twofurtheroptionscanbeselected:normal
standby mode and deep standby mode.
- The main CR PLL clock frequency becomes 10 MHz
2% when the PLL multiplication rate is 2.5.
- The main CR PLL clock frequency becomes 12 MHz
2% when the PLL multiplication rate is 3.
- The main CR PLL clock frequency becomes 16 MHz
2% when the PLL multiplication rate is 4.
❐ Selectable subclock source
• Suboscillation clock (32.768 kHz)
• External clock (32.768 kHz)
• Sub-CR clock (Typ: 100 kHz, Min: 50 kHz, Max: 150 kHz)
■ I/O port
❐ LQF044 (number of I/O ports: 41)
• General-purpose I/O ports (CMOS I/O):37
• General-purpose I/O ports (N-ch open drain):4
❐ LQA048, LQC052, WNR048 (number of I/O ports: 45)
• General-purpose I/O ports (CMOS I/O):41
• General-purpose I/O ports (N-ch open drain):4
■ Timer
❐ 8/16-bit composite timer × 2 channels
❐ 8/16-bit PPG × 3 channels
❐ 16-bit PPG timer × 1 channel (can work independently or
together with the multi-pulse generator)
■ On-chip debug
❐ 1-wire serial control
❐ 16-bit reload timer × 1 channel (can work independently or
together with the multi-pulse generator)
❐ Time-base timer × 1 channel
❐ Watch prescaler × 1 channel
❐ Serial writing supported (asynchronous mode)
■ Hardware/software watchdog timer
❐ Built-in hardware watchdog timer
❐ Built-in software watchdog timer
■ UART/SIO × 1 channel
❐ Full duplex double buffer
❐ Capable of clock asynchronous (UART) serial data transfer
and clock synchronous (SIO) serial data transfer
■ Power-on reset
❐ A power-on reset is generated when the power is switched
on.
■ I2C bus interface × 1 channel
❐ Built-in wake-up function
■ Low-voltage detection (LVD) reset circuit
■ Multi-pulse generator (MPG) (for DC motor control) × 1 channel
❐ 16-bit reload timer × 1 channel
❐ 16-bit PPG timer × 1 channel
❐ The LVD function is enabled by default. For details, see “20.2
Recommended Operating Conditions” in
“Electrical Characteristics”.
❐ The LVD function can be controlled through software.
Cypress Semiconductor Corporation
Document Number: 002-04692 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 27, 2017
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