MB90360E Series
F2MC-16LX 16-bit Microcontroller
Datasheet
The MB90360E-series, loaded 1 channel FULL-CAN* interface and Flash ROM, is general-purpose Cypress 16-bit microcontroller
designing for automotive and industrial applications. Its main feature is the on-board CAN Interfaces, which conform to Ver 2.0 Part
A and Part B, while supporting a very flexible message buffer scheme and so offering more functions than a normal FULL-CAN
approach. With the new 0.35m CMOS technology, Cypress now offers on-chip Flash ROM program memory up to 64 Kbytes.
The power supply (3 V) is supplied to the MCU core from an internal regulator circuit. This creates a major advantage in terms of EMI
and power consumption.
The internal PLL clock frequency multiplier provides an internal 42 ns instruction execution time from an external 4 MHz clock. Also,
main and sub clock can be monitored independently using the clock supervisor function.
The unit features a 4-channel input capture unit 1 channel 16-bit free running timer, 2-channel LIN-UART, and 16-channel 8/10-bit
A/D converter as the peripheral resource.
*: Controller Area Network (CAN) - License of Robert Bosch GmbH
Features
Clock
Powerful interrupt function
■ Built-in PLL clock frequency multiplication circuit
■ Powerful 8-level, 34-condition interrupt feature
■ Up to 8 channels external interrupts are supported
■ Selection of machine clocks (PLL clocks) is allowed among
frequency division by 2 on oscillation clock and multiplication
of 1 to 6 times of oscillation clock (for 4 MHz oscillation clock,
4 MHz to 24 MHz)
Automatic data transfer function independent of
CPU
Expanded intelligent I/O service function (EI2OS) : up to 16
channels
■ Operation by sub clock : internal operating clock frequency: up
to 50 kHz (for operating with 100 kHz oscillation clock divided
two and devices without S-suffix only) is available
Low power consumption (standby) mode
■ Minimum execution time of instruction: 42 ns (when operating
with 4-MHz oscillation clock and 6-time multiplied PLL clock)
■ Sleep mode (a mode that halts CPU operating clock)
■ Main timer mode (timebase timer mode that is transferred from
main clock mode)
Clock supervisor (MB90x367x only)
■ Main clock or sub clock is monitored independently
Instruction system best suited to controller
■ PLL timer mode (timebase timer mode that is transferred from
PLL clock mode)
■ Watch mode (a mode that operates sub clock and watch timer
only, devices without S-suffix)
■ 16 Mbytes CPU memory space
■ 24-bit internal addressing
■ Stop mode (a mode that stops oscillation clock and sub clock)
■ Wide choice of data types (bit, byte, word, and long word)
■ Wide choice of addressing modes (23 types)
■ CPU blocking operation mode
Process
■ Enhanced multiply-divide instructions with sign and RETI
instructions
CMOS technology
I/O port
■ Enhanced high-precision computing with 32-bit accumulator
General purpose input/output port (CMOS output) :
- 34 ports (devices without S-suffix)
- 36 ports (devices with S-suffix)
Instruction system compatible with high-level
language (C language) and multitask
■ Employing system stack pointer
■ Enhanced various pointer indirect instructions
■ Barrel shift instructions
Sub clock pin (X0A and X1A)
■ Provided(usedforexternaloscillation), deviceswithoutS-suffix
■ Not provided, devices with S-suffix
Timer
Increased processing speed
4-byte instruction queue
■ Timebase timer, watch timer (device without S-suffix) ,
watchdog timer: 1 channel
Cypress Semiconductor Corporation
Document Number: 002-04496 Rev. *A
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198 Champion Court
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San Jose, CA 95134-1709
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408-943-2600
Revised April 19, 2016