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MB87M2141 PDF预览

MB87M2141

更新时间: 2024-11-20 22:24:07
品牌 Logo 应用领域
富士通 - FUJITSU 解码器
页数 文件大小 规格书
2页 83K
描述
MPEG-2 Decoder for Set-Top-Boxes

MB87M2141 技术参数

生命周期:Obsolete包装说明:,
Reach Compliance Code:unknown风险等级:5.84
Base Number Matches:1

MB87M2141 数据手册

 浏览型号MB87M2141的Datasheet PDF文件第2页 
Product Profile  
SmartMPEGTM  
January 2003  
Edition 1.00  
MB87M2141  
FME/MM/PP/0103  
MPEG-2 Decoder for Set-Top-Boxes  
INTRODUCTION:  
FEATURES  
The SmartMPEGTM is an integrated set-top-box  
decoder. As a major component of a digital video  
broadcast (DVB) set-top-box or IDTV this device  
uses Fujitsu’s industry-leading Cx81 CMOS  
technology (0.18µm).  
It incorporates an ARC Tangent A4 RISC core  
(@130MHz), two transport stream demultiplexers  
with integrated DVB descramblers, a PAL/NTSC  
digital video encoder and a display controller, which  
overlays up to four layers of OSD. This set-top-box  
decoder consists of a shared memory interface for  
CPU and for MPEG decoding. The universal  
processor interface allows connection to FLASH,  
hard disk drives and other asynchronous devices.  
The minimum SDRAM required is one 64Mbit  
device using 16bit data bus.  
MPEG2 video ISO/IEC 13818-2 (MP@ML...SP@ML)  
MPEG audio layer 1/2  
32-bit RISC CPU (ARC Tangent A4 @130MHz)  
4K I-cache / 2K D-cache  
Three timers / watchdog / power-down mode  
Shared memory interface (SDRAM, 16/32 bit data),  
64Mbit...1Gbit  
Universal processor interface (IDE, NAND/NOR  
FLASH & Common Interface)  
Two transport stream decoders (decoding/recording)  
including DVB descrambler  
Flexible MPEG video resizing (factor 1/16 to 2)  
Display controller with up to four true colour graphic or  
CLUT layers  
Teletext / WSS / CC / VBID insertion  
PAL/NTSC digital encoder  
RGB De-matrix (RGB or YCrCb output)  
Control of brightness, contrast and colour saturation of  
RGB and YCrCb output  
The SmartMPEGTM is the 3rd generation of  
Fujitsu’s MPEG decoder, the successor to the  
MB87L2250. With the MB87L2250, Fujitsu offered a  
set-top-box chip, which enabled very low end  
product cost. Its successor, the SmartMPEGTM  
incorporates all the features which are required for  
standard set-top-boxes. This high level of  
integration makes it ideally suited for todays  
interactive set-top-box applications.  
Furthermore the Fujitsu Application Programming  
Interface (FAPI) ensures a short time-to-market by  
making the software development easier. The FAPI  
is the programming interface for Fujitsu DVB  
components as well as easing migration to future  
devices.  
5 video DAC’s @ 10bit  
ITU-R 656 video input/output (shared with TS2 input)  
S/P DIF output for PCM/AC3/MPEG  
UART / Smart Card IF / I2C / GPIO  
7-segment LED controller for 4 digits  
Infra Red receiver / transmitter  
PWM Output  
On-chip DPLL, requiring only 27.0MHz crystal  
Bootable from NOR Flash or I2C  
FPT-208P-M06 (LQFP-Package)  
Ambient Temperature Range (Std Pkg): 0oC to +70oC  
Advanced Technology: Fujitsu CMOS Cx81 (0.18µm)  
1.8 volt device with 3.3 volt I/O  
Power consumption: typ. 800mW  
S h a re d M e m o ry  
S /P -D IF  
A n a lo g O /P :  
(D o lb y D ig . B its tre a m )  
I2 S (A u d io )  
C V B S , Y C , R G B  
IT U -R 6 5 6 Y C R C B , A u d io R /L  
S D R A M  
(64 M b it 1 G b it)  
IT U -R 6 5 6  
1 6  
/ 32 b it  
D A C 1  
D A C 2  
A R C @ 130.5M H z  
T angent-A 4  
D is p la y  
C o n tro lle r  
(4 L a y er)  
D ig ita l  
E n c o d e r  
(P A L /N T S C )  
R e s izin g  
T X T In s e rtio n  
D A C 3  
D A C 4  
D A C 5  
S h a re d  
M e m o ry  
In te rfa c e  
M P E G -2 V id e o D e c o d e r  
M P E G A u d io D e c o d er  
S /P -D IF O u tp u t U n it  
4 K  
2 K  
W
a tc h -  
I-C a c h e  
D -C a c h e  
D o g  
W S S  
In s e rtio n  
/
V P S  
C C /V B ID  
In s e rtio n  
A d ju s ta b le  
R G B D e -M atrix  
IT U -R 65 6  
O u tp u t  
P o w e r-  
D o w n  
IR Q  
C T R L  
3
T im e rs  
S m a rtM P E G In te rn a l B u s  
@
1 3 0 .5 M H z  
H D D /ID E  
C T R L  
B o o t  
R O M  
D P L L  
B u ffe r M g r  
IR R x  
IR T x  
G P IO  
G P I  
G P O  
C h ip S e le c t  
D V B D e sc ra m b le rs  
T S D e m u ltip le x ers  
C T R L  
S m a rt  
C a rd  
7 -S e g  
C T R L  
T S 3  
U niversal  
P rocessor  
Interface  
I2 C  
U A R T  
P W M  
in te rn  
T S 1  
T S 2  
P a r/S e r  
N O R  
H D D  
/
N A N D F la s h  
ID E C I  
IR Q  
U A R T  
/
I2 C  
/
S m a rt C a rd  
IR O u t  
G P IO 7 -S eg m e n t C trl  
P W M / K e yB o a rd M o n  
/
P a r/S e r  
2 7 .0 M H z  
/
IR In  
/
/
/
Copyright © 2003 Fujitsu Microelectronics Europe GmbH  
Preliminary  
Page 1 of 2  
Disclaimer: The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before  
ordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.  

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