2.3W, High-Power Class D Audio Subsystem
with DirectDrive Headphone Amplifiers
Charge-Pump Capacitor Selection
Use capacitors with an ESR less than 100mΩ for opti-
mum performance. Low-ESR ceramic capacitors mini-
mize the output resistance of the charge pump. Most
surface-mount ceramic capacitors satisfy the ESR
requirement. For best performance over the extended
temperature range, select capacitors with an X7R dielec-
tric or better. Table 12 lists suggested manufacturers.
parasitic trace resistance. Large traces also aid in mov-
ing heat away from the package. Proper grounding
improves audio performance, minimizes crosstalk
between channels, and prevents any switching noise
from coupling into the audio signal. Connect PGND and
GND together at a single point on the PCB. Route all
traces that carry switching transients away from GND
and the traces/components in the audio signal path.
Connect all of the power-supply inputs (CPV , V
,
DD
DD
MAX796
Flying Capacitor (C1)
The value of the flying capacitor (C1) affects the output
resistance of the charge pump. A C1 value that is too
small degrades the device’s ability to provide sufficient
current drive, which leads to a loss of output voltage.
Increasing the value of C1 reduces the charge-pump out-
put resistance to an extent. Above 1µF, the on-resistance
of the switches and the ESR of C1 and C2 dominate.
and PV ) together. Bypass CPV
with a 1µF capaci-
DD
DD
tor to CPGND. Bypass V
GND. Bypass PV
with a 1µF capacitor to
with a 1µF capacitor in parallel with
DD
DD
a 0.1µF capacitor to PGND. Place the bypass capaci-
tors as close as possible to the MAX9796. Place a bulk
capacitor between PV
and PGND, if needed.
DD
Use large, low-resistance output traces. Current drawn
from the outputs increase as load impedance decreas-
es. High output trace resistance decreases the power
delivered to the load. Large output, supply, and GND
traces allow more heat to move from the MAX9796 to the
PCB, decreasing the thermal impedance of the circuit.
Output Capacitor (C2)
The output capacitor value and ESR directly affect the
ripple at CPV . Increasing the value of C2 reduces
SS
output ripple. Likewise, decreasing the ESR of C2
reduces both ripple and output resistance. Lower
capacitance values can be used in systems with low
maximum output power levels. See the Output Power
vs. Load Resistance and Charge-Pump Capacitor Size
graph in the Typical Operating Characteristics.
UCSP Applications Information
For the latest application details on UCSP construction,
dimensions, tape carrier information, PCB techniques,
bump-pad layout, and recommended reflow tempera-
ture profile, as well as the latest information of reliability
testing results, refer to Application Note: UCSP—A
Wafer-Level Chip-Scale Package available on Maxim’s
website at www.maxim-ic.com/ucsp.
CPV
Bypass Capacitor (C3)
DD
The CPV
bypass capacitor (C3) lowers the output
DD
impedance of the power supply and reduces the
impact of the MAX9796’s charge-pump switching tran-
sients. Bypass CPV
physically close to the CPV
for C3 that is equal to C1.
with C3 to PGND and place it
DD
UCSP Thermal Consideration
When operating at maximum output power, the UCSP
thermal dissipation can become a limiting factor. The
UCSP package does not dissipate heat as efficiently as
packages with a thermal pad. As a result, in some
applications, the thermal performance of the package
may limit performance.
and PGND. Use a value
DD
Supply Bypassing, Layout, and Grounding
Proper layout and grounding are essential for optimum
performance. Use large traces for the power-supply
inputs and amplifier outputs to minimize losses due to
Table 12. Suggested Capacitor Manufacturers
SUPPLIER
Taiyo Yuden
TDK
PHONE
FAX
WEBSITE
www.t-yuden.com
www.component.tdk.com
800-348-2496
847-803-6100
847-925-0899
847-390-4405
Chip Information
PROCESS: BiCMOS
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