Datasheet > MAX9396

MAX9396

更新时间： 2024-11-24 11:14:19

品牌	Logo	应用领域
美信 - MAXIM		解复用器
页数	文件大小	规格书
13页	164K
描述
2:1 Multiplexer and 1:2 Demultiplexer with Loopback

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MAX9396 数据手册

19-0736; Rev 0; 1/07

2:1 Multiplexer and 1:2 Demultiplexer

with Loopback

General Description

Features

The MAX9396 consists of a 2:1 multiplexer and a 1:2

demultiplexer with loopback. The multiplexer section

(channel B) accepts two differential inputs and gener-

ates a single differential output. The demultiplexer sec-

tion (channel A) accepts a single differential input and

generates two parallel differential outputs. The

MAX9396 features a loopback mode that connects the

input of channel A to the output of channel B and con-

nects the selected input of channel B to the outputs of

channel A.

♦ Guaranteed 1.25Gbps Operation with 450mV (min)

Differential Output Swing

♦ Integrated 100Ω Resistors on Differential Inputs

♦ Simultaneous Loopback Control

♦ 2ps

(max) Random Jitter

(RMS)

♦ AC Specifications Guaranteed for 150mV

Differential Input

♦ Signal Inputs Accept Any Differential Signals with

The differential inputs of the MAX9396 accept

CML/LVPECL levels and can also accept LVDS inputs

= +0.6V to (V

- 0.05V)

with common-mode voltages from +0.6V to (V

♦ LVDS Outputs for Clock or High-Speed Data

♦ Low-Level Input Fail-Safe Detection

♦ +3.0V to +3.6V Supply Voltage Range

♦ LVCMOS/LVTTL Logic Inputs

0.05V). The differential outputs are LVDS compatible

and drive 100Ω loads.

Three LVCMOS/LVTTL logic inputs control the internal

connections between inputs and outputs, one for the

multiplexer portion of channel B (BSEL), and the other

two for loopback control of channels A and B (LB_SELA

and LB_SELB). Independent enable inputs for each dif-

ferential output pair provide additional flexibility.

Ordering Information

Fail-safe circuitry forces the outputs to a differential low

condition for undriven inputs or when the common-

mode voltage is below +0.6V.

PIN-

PACKAGE

PKG

CODE

PART

TEMP RANGE

MAX9396EHJ+ -40°C to +85°C

32 TQFP

H32-1

Ultra-low 57ps

(typ) pseudorandom bit sequence

P-P

+Denotes a lead-free package.

(PRBS) jitter ensures reliable communications in high-

speed links that are highly sensitive to timing error,

especially those incorporating clock-and-data recovery,

or serializers and deserializers. The high-speed switch-

ing performance guarantees 1.25Gbps operation and

less than 87ps (max) skew between channels.

Typical Operating Circuit

+3.0V TO

+3.6V

0.1µF

= 50Ω

0.01µF

The MAX9396 is available in a 32-pin TQFP package

and is specified over the -40°C to +85°C extended tem-

perature range.

= 50Ω

INA

OUTA0

100Ω

OUTA0

OUTA1

= 50Ω

MAX9396

LVDS

RECEIVER

Applications

INB0

INB1

High-Speed Telecom/Datacom Equipment

Central Office Backplane Clock Distribution

DSLAMs

= 50Ω

OUTA1

OUTB

ENA0

ENA1

ENB

Protection Switching

OUTB

= 50Ω

LVCMOS/LVTTL

LOGIC INPUTS

Fault-Tolerant Systems

LB_SELA

LB_SELB

BSEL

GND GND GND GND

Pin Configuration and Functional Diagram appear at end of

data sheet.

________________________________________________________________ Maxim Integrated Products

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

12 3 4 5 6 7...13

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与MAX9396相关器件

型号	品牌	获取价格	描述	数据表
MAX9396EHJ	MAXIM	获取价格	2:1 Multiplexer and 1:2 Demultiplexer with Loopback
MAX93K800B	VISHAY	获取价格	MAX93K800B 5 PPM
MAX9400	MAXIM	获取价格	Quad Differential LVECL/LVPECL Buffer/Receivers
MAX9400EGJ	MAXIM	获取价格	Quad Differential LVECL/LVPECL Buffer/Receivers
MAX9400EHJ	MAXIM	获取价格	Quad Differential LVECL/LVPECL Buffer/Receivers
MAX9400EHJ+	MAXIM	获取价格	暂无描述
MAX9400EHJ+T	MAXIM	获取价格	Line Transceiver, 4 Func, 4 Driver, 4 Rcvr, BIPolar, PQFP32, 5 X 5 MM, 1 MM HEIGHT, TQFP-3
MAX9400EHJ-T	MAXIM	获取价格	Line Transceiver, 4 Func, 4 Driver, 4 Rcvr, BIPolar, PQFP32, 5 X 5 MM, 1 MM HEIGHT, TQFP-3
MAX9400EVKIT	MAXIM	获取价格	Evaluation Kit for the MAX9400/MAX9401/MAX9402/MAX9403/MAX9404/MAX9405
MAX9401	MAXIM	获取价格	Quad ECL/PECL Differential Buffers/Receivers

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