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MAX9393 PDF预览

MAX9393

更新时间: 2023-12-20 18:44:44
品牌 Logo 应用领域
亚德诺 - ADI 开关
页数 文件大小 规格书
14页 186K
描述
任意逻辑至LVDS、双路、2 x 2交叉点开关

MAX9393 数据手册

 浏览型号MAX9393的Datasheet PDF文件第6页浏览型号MAX9393的Datasheet PDF文件第7页浏览型号MAX9393的Datasheet PDF文件第8页浏览型号MAX9393的Datasheet PDF文件第10页浏览型号MAX9393的Datasheet PDF文件第11页浏览型号MAX9393的Datasheet PDF文件第12页 
Anything-to-LVDS Dual 2 x 2  
Crosspoint Switches  
V
V
V
V
OUT_0  
OUT_0  
OUT_1  
OUT_1  
V
= 0  
V
= 0  
OD  
OD  
IN_0  
IN_1  
OUT_0  
OUT_1  
t
t
CCS  
CCS  
V
OD  
= 0  
V
OD  
= 0  
2 x 2 CROSSPOINT  
V
= V  
- V  
OD  
OUT_ _ OUT_ _  
IN_0  
IN_1  
t
MEASURED WITH _SEL0 = _SEL1 = HIGH OR LOW  
(1:2 SPLITTER CONFIGURATION).  
CCS  
OUT_0 OR OUT_1  
Figure 6. Output Channel-to-Channel Skew  
2:1 MUX  
Detailed Description  
OUT_0  
OUT_1  
The LVDS interface standard provides a signaling  
method for point-to-point communication over a con-  
trolled-impedance medium as defined by the ANSI  
TIA/EIA-644 standard. LVDS utilizes a lower voltage  
swing than other communication standards, achieving  
higher data rates with reduced power consumption,  
while reducing EMI emissions and system susceptibility  
to noise.  
IN_0 OR IN_1  
1:2 SPLITTER  
IN_0  
IN_1  
OUT_0  
OUT_1  
The MAX9392/MAX9393 1.5GHz dual 2 x 2 crosspoint  
switches optimize high-speed, low-power, point-to-  
point interfaces. The MAX9392 accepts LVDS and  
HSTL signals, while the MAX9393 accepts LVPECL and  
CML signals. Both devices route the input signals to  
either or both LVDS outputs.  
DUAL REPEATER  
When configured as a 1:2 splitter, the outputs repeat  
the selected inputs. This configuration creates copies  
of signals for protection switching. When configured as  
a repeater, the device operates as a two-channel  
buffer. Repeating restores signal amplitude, allowing  
isolation of media segments or longer media drive.  
When configured as a 2:1 mux, select primary or back-  
up signals to provide a protection-switched, fault-toler-  
ant application.  
Figure 7. Programmable Configurations  
Select Function  
The _SEL_ logic inputs control the input and output sig-  
nal connections. Two logic inputs control the signal rout-  
ing for each channel. _SEL0 and _SEL1 allow the  
devices to be configured as a differential crosspoint  
switch, 2:1 mux, dual repeater, or 1:2 splitter (Figure 7).  
See Table 1 for mode-selection settings (insert A or B for  
the _). Channels A and B possess separate select  
inputs, allowing different configurations for each channel.  
Input Fail-Safe  
The differential inputs of the MAX9392/MAX9393 pos-  
sess internal fail-safe protection. Fail-safe circuitry  
forces the outputs to a differential low condition for  
undriven inputs or when the common-mode voltage  
exceeds the specified range. The MAX9392 provides  
high-level input fail-safe detection for LVDS, HSTL, and  
other GND-referenced differential inputs. The MAX9393  
provides low-level input fail-safe detection for LVPECL,  
Enable Function  
The EN_ _ logic inputs enable and disable each set of  
differential outputs. Connect EN_ 0 to V  
to enable  
CC  
the OUT_0/OUT_0 differential output pair. Connect  
EN_0 to GND to disable the OUT_0/OUT_0 differential  
output pair. The differential output pairs assert to a dif-  
ferential low condition when disabled.  
CML, and other V -referenced differential inputs.  
CC  
_______________________________________________________________________________________  
9

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