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MAX9220ETM PDF预览

MAX9220ETM

更新时间: 2024-02-29 05:14:02
品牌 Logo 应用领域
美信 - MAXIM 线路驱动器或接收器驱动程序和接口接口集成电路
页数 文件大小 规格书
18页 902K
描述
Programmable DC-Balance 21-Bit Deserializers

MAX9220ETM 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP,针数:48
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.79
差分输出:NO输入特性:DIFFERENTIAL
接口集成电路类型:LINE RECEIVER接口标准:EIA-644; TIA-644
JESD-30 代码:R-PDSO-G48长度:12.5 mm
功能数量:4端子数量:48
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
接收器位数:4座面最大高度:1.1 mm
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:6.1 mmBase Number Matches:1

MAX9220ETM 数据手册

 浏览型号MAX9220ETM的Datasheet PDF文件第9页浏览型号MAX9220ETM的Datasheet PDF文件第10页浏览型号MAX9220ETM的Datasheet PDF文件第11页浏览型号MAX9220ETM的Datasheet PDF文件第13页浏览型号MAX9220ETM的Datasheet PDF文件第14页浏览型号MAX9220ETM的Datasheet PDF文件第15页 
Programmable DC-Balance  
21-Bit Deserializers  
MAX9209  
MAX9211  
MAX9213  
MAX9210  
MAX9212  
MAX9214  
MAX9216  
MAX9220  
MAX9222  
HIGH-FREQUENCY CERAMIC  
SURFACE-MOUNT CAPACITORS  
MAX9215  
TxOUT  
RxIN  
7
7
7
7
7
7
100Ω  
(7 + 2):1  
(7 + 2):1  
(7 + 2):1  
PLL  
1:(9 - 2)  
1:(9 - 2)  
1:(9 - 2)  
PLL  
100Ω  
100Ω  
100Ω  
TxIN  
RxOUT  
PWRDWN  
TxCLK IN  
PWRDWN  
RxCLK OUT  
TxCLK OUT  
RxCLK IN  
21:3 SERIALIZER  
3:21 DESERIALIZER  
Figure 13. Four Capacitors per Link, AC-Coupled, DC-Balanced Mode  
Jitter due to droop is proportional to the droop and  
transition time:  
Fail-Safe  
The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/  
MAX9222 have fail-safe LVDS inputs in non-DC-bal-  
anced mode (Figure 1). Fail-safe drives the outputs low  
when the corresponding LVDS input is open, undriven  
and shorted, or undriven and parallel terminated. The  
fail-safe on the LVDS clock input drives all outputs low.  
Fail-safe does not operate in DC-balanced mode.  
t = t x D (Eq 2)  
J
T
where:  
t = jitter (s).  
J
t = transition time (s) (0 to 100%).  
T
D = droop (% of signal amplitude).  
Jitter due to 2% droop and assumed 1ns transition time is:  
Input Bias and Frequency Detection  
In DC-balanced mode, the inverting and noninverting  
LVDS inputs are internally connected to +1.2V through  
42k(min) to provide biasing for AC-coupling (Figure 1).  
A frequency-detection circuit on the clock input detects  
when the input is not switching, or is switching at low  
frequency. In this case, all outputs are driven low. To  
prevent switching due to noise when the clock input is  
not driven, bias the clock input to differential +15mV by  
connecting a 10k1% pullup resistor between the  
t = 1ns x 0.02  
J
t = 20ps  
J
The transition time in a real system depends on the fre-  
quency response of the cable driven by the serializer.  
The capacitor value decreases for a higher frequency  
parallel clock and for higher levels of droop and jitter.  
Use high-frequency, surface-mount ceramic capacitors.  
Equation 1 altered for four series capacitors (Figure 13) is:  
C = - (4 x t x DSV) / (ln (1 - D) x (R + R )) (Eq 3)  
noninverting input and V , and a 10k1% pulldown  
B
T
O
CC  
resistor between the inverting input and ground. These  
12 ______________________________________________________________________________________  

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