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MAX9220ETM

更新时间： 2024-02-25 22:44:21

品牌	Logo	应用领域
美信 - MAXIM		线路驱动器或接收器驱动程序和接口接口集成电路
页数	文件大小	规格书
18页	902K
描述
Programmable DC-Balance 21-Bit Deserializers

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技术参数
数据手册

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MAX9220ETM 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	TSSOP
包装说明：	TSSOP,	针数：	48
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.79
差分输出：	NO	输入特性：	DIFFERENTIAL
接口集成电路类型：	LINE RECEIVER	接口标准：	EIA-644; TIA-644
JESD-30 代码：	R-PDSO-G48	长度：	12.5 mm
功能数量：	4	端子数量：	48
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	NOT SPECIFIED	认证状态：	Not Qualified
接收器位数：	4	座面最大高度：	1.1 mm
最大供电电压：	3.6 V	最小供电电压：	3 V
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	6.1 mm	Base Number Matches：	1

MAX9220ETM 数据手册

Programmable DC-Balance

21-Bit Deserializers

bias resistors, along with the 100Ω 1% tolerance ter-

Power-Supply Bypassing

There are separate on-chip power domains for digital

circuits, outputs, PLL, and LVDS inputs. Bypass each

mination resistor, provide +15mV of differential input.

However, the +15mV bias causes degradation of

RSKM proportional to the slew rate of the clock input.

For example, if the clock transitions 250mV in 500ps,

the slew rate of 0.5mV/ps reduces RSKM by 30ps.

, V

, PLL V , and LVDS V

pin with high-fre-

CC CCO

quency, surface-mount ceramic 0.1µF and 0.001µF

capacitors in parallel as close to the device as possi-

ble, with the smallest value capacitor closest to the

supply pin.

Unused LVDS Data Inputs

In non-DC-balanced mode, leave unused LVDS data

inputs open. In non-DC balanced mode, the input fail-

safe circuit drives the corresponding outputs low and no

pullup or pulldown resistors are needed. In DC-balanced

mode, at each unused LVDS data input, pull the inverting

Cables and Connectors

Interconnect for LVDS typically has a differential imped-

ance of 100Ω. Use cables and connectors that have

matched differential impedance to minimize impedance

discontinuities.

input up to V

using a 10kΩ resistor, and pull the nonin-

verting input down to ground using a 10kΩ resistor. Do

not connect a termination resistor. The pullup and pull-

down resistors drive the corresponding outputs low and

prevent switching due to noise.

Twisted-pair and shielded twisted-pair cables offer

superior signal quality compared to ribbon cable and

tend to generate less EMI due to magnetic field cancel-

ing effects. Balanced cables pick up noise as common

mode, which is rejected by the LVDS receiver.

PWRDWN

Driving PWRDWN low puts the outputs in high imped-

ance, stops the PLL, and reduces supply current to

50µA or less. Driving PWRDWN high drives the outputs

low until the PLL locks. The outputs of two deserializers

can be bused to form a 2:1 mux with the outputs con-

trolled by PWRDWN. Wait 100ns between disabling one

deserializer (driving PWRDWN low) and enabling the

second one (driving PWRDWN high) to avoid con-

tention of the bused outputs.

Board Layout

Keep the LVTTL/LVCMOS outputs and LVDS input sig-

nals separated to prevent crosstalk. A four-layer PC

board with separate layers for power, ground, LVDS

inputs, and digital signals is recommended.

IEC 61000-4-2 Level 4 ESD Protection

The IEC 61000-4-2 standard specifies ESD tolerance

for electronic systems. The IEC 61000-4-2 model

(Figure 14) specifies a 150pF capacitor that is dis-

charged into the device through a 330Ω resistor. The

MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/

MAX9222 LVDS inputs are rated for IEC 61000-4-2

level 4 (±8kV contact discharge and 15kV air dis-

charge). IEC 61000-4-2 discharges higher peak current

and more energy than the HBM due to the lower series

resistance and larger capacitor. The HBM (Figure 15)

specifies a 100pF capacitor that is discharged into the

device through a 1.5kΩ resistor. All pins are rated for

5kV HBM.

Input Clock and PLL Lock Time

There is no required timing sequence for the applica-

tion or reapplication of the parallel rate clock (RxCLK

IN) relative to PWRDWN, or to a power-supply ramp for

proper PLL lock. The PLL lock time is set by an internal

counter. The maximum time to lock is 32,800 clock

periods. Power and clock should be stable to meet the

lock time specification. When the PLL is locking, the

outputs are low.

1MΩ

1.5kΩ

50Ω TO 100Ω

330kΩ

CHARGE-CURRENT-

LIMIT RESISTOR

DISCHARGE

RESISTANCE

CHARGE-CURRENT-

LIMIT RESISTOR

DISCHARGE

RESISTANCE

HIGH-

VOLTAGE

HIGH-

VOLTAGE

DEVICE

UNDER

TEST

DEVICE

UNDER

TEST

100pF

150pF

STORAGE

CAPACITOR

STORAGE

CAPACITOR

SOURCE

Figure 14. IEC 61000-4-2 Contact Discharge ESD Test Circuit

______________________________________________________________________________________ 13

Figure 15. Human Body ESD Test Circuit

1...10 11 121314 15 16...18

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与MAX9220ETM相关器件

型号	品牌	描述	获取价格	数据表
MAX9220EUM	MAXIM	Programmable DC-Balance 21-Bit Deserializers	获取价格
MAX9220EUM+T	MAXIM	暂无描述	获取价格
MAX9220EUM+TD	MAXIM	Line Receiver, 4 Func, 4 Rcvr, CMOS, PDSO48, 6.10 MM, ROHS COMPLIANT, MO-153ED, TSSOP-48	获取价格
MAX9220EUM-D	MAXIM	Line Receiver, 4 Func, 4 Rcvr, CMOS, PDSO48, 6.10 MM, MO-153ED, TSSOP-48	获取价格
MAX9220EUM-TD	MAXIM	Line Receiver, 4 Func, 4 Rcvr, CMOS, PDSO48, 6.10 MM, MO-153ED, TSSOP-48	获取价格
MAX9222	MAXIM	Programmable DC-Balance 21-Bit Deserializers	获取价格

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