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MAX9160

更新时间： 2024-11-17 22:35:03
品牌 Logo 应用领域
美信 - MAXIM 时钟驱动器
页数 文件大小 规格书
13页 348K
描述
LVDS or LVTTL/LVCMOS Input to 14 LVTTL/LVCMOS Output Clock Driver

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MAX9160 数据手册

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19-2392; Rev 0; 4/02  
LVDS or LVTTL/LVCMOS Input to  
14 LVTTL/LVCMOS Output Clock Driver  
General Description  
Features  
The MAX9160 125MHz, 14-port LVTTL/LVCMOS clock  
driver repeats the selected LVDS or LVTTL/LVCMOS  
input on two output banks. Each bank consists of seven  
LVTTL/LVCMOS series terminated outputs and a bank  
enable. The LVDS input has a fail-safe function. The  
MAX9160 has a propagation delay that can be adjusted  
using an external resistor to set the bias current for an  
internal delay cell. The LVTTL/LVCMOS outputs feature  
200ps maximum output-to-output skew and 100ps maxi-  
mum added peak-to-peak jitter.  
ꢀ LVDS or LVTTL/LVCMOS Input Selection  
ꢀ LVDS Input Fail-Safe Sets Outputs High for Open,  
Undriven Short, or Undriven Parallel Termination  
ꢀ Two Output Banks with Separate Bank Enables  
ꢀ Integrated Output Series Termination for 60Ω  
Lines  
ꢀ 200ps (max) Output-to-Output Skew  
ꢀ
100ps (max) Peak-to-Peak Added Output Jitter  
The MAX9160 is designed to operate with a 3.3V sup-  
ply voltage over the extended temperature range of  
-40°C to +85°C. This device is available in 28-pin  
exposed- and nonexposed-pad TSSOP and 32-lead  
5mm x 5mm QFN packages.  
ꢀ 42% to 58% Output Duty Cycle at 125MHz  
ꢀ Guaranteed 125MHz Operating Frequency  
ꢀ LVDS Input Is High Impedance with V  
= 0V  
CC  
or Open (Hot Swappable)  
ꢀ 28-Pin Exposed- and Nonexposed-Pad TSSOP  
or 32-Lead QFN Packages  
ꢀ -40°C to +85°C Operating Temperature  
Applications  
Digital Cross-Connects  
DSLAMs  
Cellular Base Stations  
Servers  
ꢀ 3.0V to 3.6V Supply Voltage  
Add/Drop Multiplexers  
Networking Equipment  
Ordering Information  
Typical Application Circuit and Functional Diagram appear  
at end of data sheet.  
PART  
TEMP RANGE  
-40°C to +85°C  
-40°C to +85°C  
-40°C to +85°C  
PIN-PACKAGE  
28 TSSOP  
MAX9160EUI  
MAX9160AEUI  
MAX9160EGJ*  
28 TSSOP-EP**  
32 QFN-EP  
Pin Configurations  
*Future product—contact factory for availability.  
**Exposed pad.  
TOP VIEW  
OUTA5  
OUTA6  
ENA  
1
2
3
4
5
6
7
8
9
28 OUTA4  
27 OUTA3  
26 GND  
Function Table  
EN_  
SEL SE_IN  
V
OUT_  
ID  
H
H
H
X
H
SEL  
25 OUTA2  
24 OUTA1  
L or  
open  
SE_IN  
H
H
H
H
X
L
H
L
MAX9160  
V
CC  
23 V  
CC  
L or  
open  
GND  
IN+  
IN-  
22 OUTA0  
21 OUTB6  
20 GND  
X
X
≥ +50mV  
≤ -50mV  
L or  
open  
GND 10  
RSET 11  
ENB 12  
19 OUTB5  
18 OUTB4  
L or  
open  
Open, undriven short, or  
undriven parallel termination  
H
X
X
H
L
17  
V
CC  
OUTB0 13  
OUTB1 14  
16 OUTB3  
15 OUTB2  
L or  
Open  
X
X
TSSOP  
V
= V  
- V  
IN-  
L = low logic level  
X = don’t care  
ID  
IN+  
H = high logic level  
Pin Configurations continued at end of data sheet.  
________________________________________________________________ Maxim Integrated Products  
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at  
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.  
1234567...13

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