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MAX7349AWG

更新时间： 2024-02-13 04:48:09

品牌	Logo	应用领域
美信 - MAXIM		开关控制器
页数	文件大小	规格书
29页	348K
描述
Microprocessor Circuit, BICMOS, PDSO24, 0.300 INCH, MS-013AD, SOIC-24

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技术参数
数据手册

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MAX7349AWG 技术参数

是否Rohs认证：	不符合	生命周期：	Active
Reach Compliance Code：	not_compliant	风险等级：	5.88
JESD-30 代码：	R-PDSO-G24	JESD-609代码：	e0
端子数量：	24	最高工作温度：	125 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP24,.4
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
电源：	2.5/3.3 V	认证状态：	Not Qualified
子类别：	Parallel IO Port	最大压摆率：	0.1 mA
表面贴装：	YES	技术：	BICMOS
温度等级：	AUTOMOTIVE	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	Base Number Matches：	1

MAX7349AWG 数据手册

2-Wire Interfaced Low-EMI Key Switch

and Sounder Controllers

8/MAX7349

I C TIMING CHARACTERISTICS

(V+ = 2.4V to 3.6V, T = T

to T

, unless otherwise noted. Typical values are at V+ = 3.3V, T = +25°C.) (Notes 1, 2)

MAX A

MIN

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Input Capacitance

(SCL, SDA, AD0)

(Notes 3, 4)

With bus timeout enabled

With bus timeout disabled

0.05

400

SCL Serial Clock Frequency

kHz

µs

SCL

BUF

Bus Free Time Between a STOP

and a START Condition

1.3

0.6

Hold Time (Repeated) START

Condition

µs

HD, STA

Repeated START Condition

Setup Time

0.6

µs

SU, STA

STOP Condition Setup Time

Data Hold Time

µs

SU, STO

(Note 5)

0.9

HD, DAT

Data Setup Time

100

1.3

0.7

SU, DAT

SCL Clock Low Period

SCL Clock High Period

LOW

HIGH

Rise Time of Both SDA and SCL

Signals, Receiving

20 +

(Notes 3, 4)

300

0.1C

Fall Time of Both SDA and SCL

Signals, Receiving

20 +

0.1C

20 +

0.1C

Fall Time of SDA Transmitting

(Notes 3, 6)

(Notes 3, 7)

(Note 3)

250

F.TX

Pulse Width of Spike Suppressed

Capacitive Load for Each Bus

Line

400

Note 1: All parameters are tested at T = +25°C. Specifications over temperature are guaranteed by design.

Note 2: All digital inputs at V+ or GND.

Note 3: Guaranteed by design.

Note 4: C = total capacitance of one bus line in pF. t and t measured between 0.8V and 2.1V.

Note 5: A master device must provide a hold time of at least 300ns for the SDA signal (referred to V of the SCL signal) to bridge

the undefined region of SCL’s falling edge.

Note 6: I

≤ 6mA. C = total capacitance of one bus line in pF. t and t measured between 0.8V and 2.1V.

Note 7: Input filters on the SDA, SCL, and AD0 inputs suppress noise spikes less than 50ns.

SINK

b R F

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