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MAX7311ATG+ PDF预览

MAX7311ATG+

更新时间： 2024-01-30 05:58:44
品牌 Logo 应用领域
恩智浦 - NXP PC信息通信管理外围集成电路
页数 文件大小 规格书
16页 376K
描述
IC,I/O PORT,16-BIT,BICMOS,LLCC,24PIN,PLASTIC

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中文翻译

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MAX7311ATG+ 技术参数

是否Rohs认证： 符合生命周期：Transferred
包装说明：QCCN, LCC24,.16SQ,20Reach Compliance Code：unknown
风险等级：5.78JESD-30 代码：S-PQCC-N24
位数：16端子数量：24
最高工作温度：125 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：QCCN
封装等效代码：LCC24,.16SQ,20封装形状：SQUARE
封装形式：CHIP CARRIER电源：2/5.5 V
认证状态：Not Qualified子类别：Parallel IO Port
表面贴装：YES技术：BICMOS
温度等级：AUTOMOTIVE端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
Base Number Matches：1

MAX7311ATG+ 数据手册

 浏览型号MAX7311ATG+的Datasheet PDF文件第7页浏览型号MAX7311ATG+的Datasheet PDF文件第8页浏览型号MAX7311ATG+的Datasheet PDF文件第9页浏览型号MAX7311ATG+的Datasheet PDF文件第11页浏览型号MAX7311ATG+的Datasheet PDF文件第12页浏览型号MAX7311ATG+的Datasheet PDF文件第13页 
2-Wire-Interfaced 16-Bit I/O Port Expander  
with Interrupt and Hot-Insertion Protection  
Data is clocked into a register on the falling edge of the  
acknowledge clock pulse. After reading the first byte,  
additional bytes may be read and reflect the content in  
the other register in the pair. For example, if input port 1  
is read, the next byte read is input port 2. An unlimited  
number of data bytes can be read in one read trans-  
mission, but the final byte received must not be  
acknowledged by the bus master.  
Input/Output Port  
When an I/O is configured as an input, FETs Q1 and Q2  
are off (Figure 10), creating a high-impedance input with  
+
a nominal 100kΩ pullup to V . All inputs are overvoltage  
protected to 5.5V, independent of supply voltage. When  
a port is configured as an output, either Q1 or Q2 is on,  
depending on the state of the output port register. When  
+
V powers up, an internal power-on reset sets all regis-  
ters to their respective defaults (Table 1).  
Interrupt (INT)  
The open-drain interrupt output, INT, activates when  
one of the port pins changes states and only when the  
pin is configured as an input. The interrupt deactivates  
when the input returns to its previous state or the input  
register is read (Figure 9). A pin configured as an out-  
put does not cause an interrupt. Each ±-bit port register  
is read independently; therefore, an interrupt caused  
by port 1 is not cleared by a read of port 2’s register.  
Input Port Registers  
The input port registers (Table 2) are read-only ports.  
They reflect the incoming logic levels of the pins,  
regardless of whether the pin is defined as an input or  
an output by the respective configuration register. A  
read of the input port 1 register latches the current  
value of I/O0–I/O7. A read of the input port 2 register  
latches the current value of I/O±–I/O15. Writes to the  
input port registers are ignored.  
Changing an I/O from an output to an input may cause  
a false interrupt to occur if the state of that I/O does not  
match the content of the input port register.  
OUTPUT PORT  
REGISTER DATA  
CONFIGURATION  
REGISTER  
V
DD  
SET  
Q1  
DATA FROM  
SHIFT REGISTER  
100kΩ  
D
Q
Q
I/O PIN  
WRITE  
CONFIGURATION  
PULSE  
CLR  
SET  
CLR  
DATA FROM  
SHIFT REGISTER  
D
Q
Q
WRITE PULSE  
Q2  
OUTPUT PORT  
REGISTER  
V
SS  
INPUT PORT  
REGISTER  
SET  
D
Q
INPUT PORT  
READ PULSE  
REGISTER DATA  
Q
CLR  
SET  
TO INT  
POWER-ON  
RESET  
POLARITY  
REGISTER  
DATA  
DATA FROM  
SHIFT REGISTER  
D
Q
Q
WRITE POLARITY  
PULSE  
CLR  
POLARITY INVERSION  
REGISTER  
Figure 10. Simplified Schematic of I/Os  
10 ______________________________________________________________________________________  
1...78910111213...16

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