Datasheet > MAX7311ATG+

MAX7311ATG+

更新时间： 2024-01-27 07:46:17

品牌	Logo	应用领域
恩智浦 - NXP		PC 信息通信管理外围集成电路
页数	文件大小	规格书
16页	376K
描述
IC,I/O PORT,16-BIT,BICMOS,LLCC,24PIN,PLASTIC

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技术参数
数据手册

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MAX7311ATG+ 技术参数

是否Rohs认证：	符合	生命周期：	Transferred
包装说明：	QCCN, LCC24,.16SQ,20	Reach Compliance Code：	unknown
风险等级：	5.78	JESD-30 代码：	S-PQCC-N24
位数：	16	端子数量：	24
最高工作温度：	125 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCN
封装等效代码：	LCC24,.16SQ,20	封装形状：	SQUARE
封装形式：	CHIP CARRIER	电源：	2/5.5 V
认证状态：	Not Qualified	子类别：	Parallel IO Port
表面贴装：	YES	技术：	BICMOS
温度等级：	AUTOMOTIVE	端子形式：	NO LEAD
端子节距：	0.5 mm	端子位置：	QUAD
Base Number Matches：	1

MAX7311ATG+ 数据手册

2-Wire-Interfaced 16-Bit I/O Port Expander

with Interrupt and Hot-Insertion Protection

SDA

SCL

START

STOP

CONDITION

Figure 3. START and STOP Conditions

SDA

SCL

DATA LINE STABLE; DATA VALID CHANGE OF DATA ALLOWED

Figure 4. Bit Transfer

START CONDITION

SCL

CLOCK PULSE FOR ACKNOWLEDGMENT

SDA

BY TRANSMITTER

SDA

BY RECEIVER

Figure 5. Acknowledge

Each transmission consists of a START condition sent by

a master, followed by the MAX7311 7-bit slave address

plus R/W bit, a register address byte, 1 or more data

bytes, and finally a STOP condition (Figure 3).

Bit Transfer

One data bit is transferred during each clock pulse.

The data on SDA must remain stable while SCL is high

(Figure 4).

START and STOP Conditions

Both SCL and SDA remain high when the interface is

not busy. A master signals the beginning of a transmis-

sion with a START (S) condition by transitioning SDA

from high to low while SCL is high. When the master

has finished communicating with the slave, it issues a

STOP (P) condition by transitioning SDA from low to

high while SCL is high. The bus is then free for another

transmission (Figure 3).

Acknowledge

The acknowledge bit is a clocked 9th bit, which the

recipient uses as a handshake receipt of each byte of

data (Figure 5). Thus, each byte transferred effectively

requires 9 bits. The master generates the 9th clock

pulse, and the recipient pulls down SDA during the

acknowledge clock pulse, such that the SDA line is sta-

ble low during the high period of the clock pulse. When

the master is transmitting to the MAX7311, the

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1...4 5 678 9 10...16

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