32-Channel Sample/Hold Amplifier
with a Single Multiplexed Input
selected multiplexer channel connects to IN, allowing the
hold capacitor to acquire the input signal. To guarantee
an accurate sample, maintain sample mode for at least
4µs. The output of the sample/hold amplifier tracks the
input after 4µs. Only the addressed channel on the
selected multiplexer samples the input; all other channels
remain in hold mode.
when ꢀ = , then A = 1, and this equation becomes
L V
(V + 0.75V)
SS
V
OUT
(V
DD
- 2.4V)
Timing Definitions
Acquisition time (t ) is the time the MAX5168 must
AQ
remain in sample mode for the hold capacitor to
acquire an accurate sample. The hold-mode settling
time (t ) is the time necessary for the output voltage to
H
Hold Mode
No matter what the condition of the other control lines,
S/H = high places the MAX5168 into an all-channel
hold mode. Hold mode disables the multiplexer and
disconnects all 32 sample/holds from the input. When a
channel is disconnected, the hold capacitor maintains
the sampled voltage at the output with a 1mV/s typical
settle to its final value. Aperture delay (t ) is the time
AP
interval required to disconnect the input from the hold
capacitor. The hold pulse width (t ) is the time the
PW
MAX5168 must remain in hold mode while the address
is changed. Data setup time (t ) is the time an
DS
address must be maintained at the digital input pins
before the address becomes valid. Data hold time (t
)
DH
droop rate (towards V ).
DD
is the time an address must be maintained after the
device is placed in hold mode (Figure 2).
Hold Step
When switching between sample mode and hold mode,
the voltage of the hold capacitor changes due to
charge injection from stray capacitance. This voltage
change, called a hold step, is minimized by limiting the
amount of stray capacitance seen by the hold capacitor.
The MAX5168 limits the hold step to 0.25mV (typ). An
output capacitor to ground can be used to filter out this
small hold-step error.
Applications Information
Multiplexing a DAC
Figure 3 shows a typical demultiplexer application.
Different digital codes are converted by the digital-to-
analog converter (DAC) and then stored on 32 different
channels of the MAX5168. The 40mV/s (max) droop
rate requires refreshing the hold capacitors every
250ms before the voltage droops by 1/2LSB for an 8-bit
DAC with a 5V full-scale voltage.
Output
The MAX5168 contains an output buffer for each multi-
plexer channel (32 total), so the hold capacitor sees a
high-impedance input that reduces the droop rate. The
capacitor droops at 1mV/s (typ) while in hold mode. The
buffer also provides a low output impedance; however,
the device contains output resistors in series with the
buffer output (Figure 1) for selected output filtering. To
provide greater design flexibility, the MAX5168 is avail-
able with an output impedance of 50 , 500 , or 1k .
Virtual 64 Output Sample/Hold
Two MAX5168s can be configured to operate as a single
64 output sample/hold. The upper and lower addressed
devices are identified by CONFIG’s logic level. Connect
the CONFIG pin of the upper device low, making its
SELECT pin active high. Connect the CONFIG pin of the
lower device high to make the SELECT pin active low.
Figure 4 shows how to configure the devices.
Output loads increase the analog supply current (I
DD
The devices now use only six address lines and a sin-
gle S/H control to decode 64 outputs. Address lines
A0–A4 from the control logic connect to ADDꢀ0–
ADDꢀ4 on both of the 32-channel devices. The A5 line
toggles the SELECT pins of both devices to select the
active one. The device that has CONFIG tied high
responds to the lower 32 addresses (000000 through
011111). The device that has CONFIG grounded
responds to the upper 32 addresses (100000 through
111111).
and I ). Excessive loading of the output(s) drastically
SS
increases power dissipation. Do not exceed the maximum
power dissipation specified in the Absolute Maximum
Ratings.
The resistor-divider formed by the output resistor (ꢀ ) and
O
load impedance (ꢀ ) scales the sampled voltage
L
(V ). Determine the output voltage (V ) as follows:
SAMP OUT_
Voltage Gain = A = ꢀ / (ꢀ + ꢀ )
V
L
L
O
✕
V
OUT_
= V
A
V
SAMP
The maximum output voltage range depends on the ana-
log supply voltages available and the scaling factor used:
✕
✕
(V + 0.75V)
SS
A
V
OUT_
(V
DD
- 2.4V)
A
V
V
8
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