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MAX5168NCCM-T PDF预览

MAX5168NCCM-T

更新时间: 2024-02-24 15:36:45
品牌 Logo 应用领域
美信 - MAXIM 放大器信息通信管理
页数 文件大小 规格书
12页 161K
描述
Sample and Hold Circuit, 1 Func, Sample, 2.5us Acquisition Time, BICMOS, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, TQFP-48

MAX5168NCCM-T 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:LFQFP,
针数:48Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.33.00.01
风险等级:5.7最长采集时间:4 µs
标称采集时间:2.5 µs放大器类型:SAMPLE AND HOLD CIRCUIT
最大模拟输入电压:7 V最小模拟输入电压:-4 V
最大下降率:0.04 V/sJESD-30 代码:S-PQFP-G48
JESD-609代码:e0长度:7 mm
标称负供电电压 (Vsup):-5 V功能数量:1
端子数量:48最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):245
认证状态:Not Qualified采样并保持/跟踪并保持:SAMPLE
座面最大高度:1.6 mm标称供电电压 (Vsup):10 V
表面贴装:YES技术:BICMOS
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7 mmBase Number Matches:1

MAX5168NCCM-T 数据手册

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32-Channel Sample/Hold Amplifier  
with a Single Multiplexed Input  
ADDR0ADDR4  
S/H  
SELECT  
CONFIG  
CS  
SW1 SW2  
SW30 SW31  
MAX5168  
OUT0  
OUT1  
IN  
OUT30  
OUT31  
Figure 1. Functional Diagram  
The SELECT and CONFIG pins allow the design of a  
virtual 64-channel device using two of the MAX5168s.  
See the Applications Information section for more infor-  
mation about 64-plus output addressing schemes.  
Detailed Description  
Digital Interface  
The MAX5168 has three logic control inputs and five  
address lines. The address lines are inputs to a demul-  
tiplexer that selects one of the 32 outputs in a standard  
addressing scheme (Table 1). The analog input is con-  
nected to the addressed sample/hold when directed by  
the control logic (Table 2).  
Sample/Hold  
The MAX5168 contains 32 buffered sample/hold circuits  
with internal hold capacitors. Internal hold capacitors  
minimize leakage current, dielectric absorption,  
feedthrough, and required board space. The value of  
the hold capacitor affects acquisition time and droop  
rate. Smaller capacitance allows faster acquisition  
times but increases the droop rate. Larger values  
increase hold acquisition time. The hold capacitor used  
in the MAX5168 provides fast 2.5µs (typ) acquisition  
time while maintaining a relatively low 1mV/s (typ)  
droop rate, making the sample/hold ideal for high-  
speed sampling.  
The three logic control lines determine the state of the  
addressed sample/hold. The normal circuit connection  
for this device is to hardwire CONFIG and SELECT to  
opposing logic voltages. When SELECT and CONFIG  
are in opposite states (one high and the other low), the  
five address lines select one of the sample/holds. Use  
the S/H line to place the selected channel into sample  
or hold mode. The other 31 channels will remain in hold  
mode.  
Sample Mode  
When SELECT and CONFIG are in opposing logic states,  
the S/H line controls the mode of operation. Sample mode  
is entered when S/H is low. During sample mode, the  
If an active-high sampling mode is desired, tie S/H and  
CONFIG low. In this case, SELECT controls the  
addressed channel with a high state putting that chan-  
nel into sample mode.  
6
_______________________________________________________________________________________  

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