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MAX509BEAP

更新时间： 2024-11-28 22:25:43
品牌 Logo 应用领域
美信 - MAXIM /
页数 文件大小 规格书
20页 235K
描述
Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs

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中文翻译

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MAX509BEAP 数据手册

 浏览型号MAX509BEAP的Datasheet PDF文件第2页浏览型号MAX509BEAP的Datasheet PDF文件第3页浏览型号MAX509BEAP的Datasheet PDF文件第4页浏览型号MAX509BEAP的Datasheet PDF文件第5页浏览型号MAX509BEAP的Datasheet PDF文件第6页浏览型号MAX509BEAP的Datasheet PDF文件第7页 
19-0155; Rev 2; 1/96  
Qu a d , S e ria l 8 -Bit DACs  
w it h Ra il-t o -Ra il Ou t p u t s  
9/MAX510  
_______________Ge n e ra l De s c rip t io n  
____________________________Fe a t u re s  
♦ Single +5V or Dual ±5V Supply Operation  
The MAX509/MAX510 are quad, serial-input, 8-bit volt-  
age-output digital-to-analog converters (DACs). They  
operate with a single +5V supply or dual ±5V supplies.  
Internal, precision buffers swing rail-to-rail. The refer-  
ence input range includes both supply rails.  
♦ Output Buffer Amplifiers Swing Rail-to-Rail  
♦ Reference Input Range Includes Both Supply Rails  
♦ Calibrated Offset, Gain, and Linearity (1LSB TUE)  
♦ 10MHz Serial Interface, Compatible with SPI, QSPI  
The MAX509 has four separate reference inputs, allow-  
ing each DAC's full-scale range to be set independently.  
20-pin DIP, SSOP, and SO packages are available. The  
MAX510 is identical to the MAX509 except it has two ref-  
erence inputs, each shared by two DACs. The MAX510  
is housed in space-saving 16-pin DIP and SO packages.  
(CPOL = CPHA = 0) and Microwire  
♦ Double-Buffered Registers for Synchronous  
Updating  
♦ Serial Data Output for Daisy-Chaining  
♦ Power-On Reset Clears Serial Interface and Sets  
All Registers to Zero  
The serial interface is double-buffered: A 12-bit input  
shift register is followed by four 8-bit buffer registers and  
four 8-bit DAC registers. A 12-bit serial word is used to  
load data into each register. Both input and DAC regis-  
ters can be updated independently or simultaneously  
with single software commands. Two additional asyn-  
chronous control pins provide simultaneous updating  
(LDAC) or clearing (CLR) of input and DAC registers.  
______________Ord e rin g In fo rm a t io n  
TUE  
(LSB)  
PART  
TEMP. RANGE PIN-PACKAGE  
MAX509ACPP  
MAX509BCPP  
MAX509ACWP  
MAX509BCWP  
MAX509ACAP  
MAX509BCAP  
MAX509BC/D  
0°C to +70°C  
0°C to +70°C  
0°C to +70°C  
0°C to +70°C  
0°C to +70°C  
0°C to +70°C  
0°C to +70°C  
20 Plastic DIP  
20 Plastic DIP  
20 Wide SO  
20 Wide SO  
20 SSOP  
±1  
±1 1/2  
±1  
The interface is compatible with MicrowireTM and SPI/  
QSPITM  
. All digital inputs and outputs are TTL/CMOS  
±1 1/2  
±1  
compatible. A buffered data output provides for read-  
back or daisy-chaining of serial devices.  
20 SSOP  
±1 1/2  
±1 1/2  
Dice*  
Ordering Information continued on last page.  
* Dice are specified at +25°C, DC parameters only.  
_______________Fu n c t io n a l Dia g ra m s  
**Contact factory for availability and processing to MIL-STD-883.  
CLR  
LDAC  
DGND  
AGND  
V
SS  
DOUT  
V
DD  
REFB REFA  
_________________P in Co n fig u ra t io n s  
MAX509  
DECODE  
CONTROL  
TOP VIEW  
OUTA  
INPUT  
REG A  
DAC  
REG A  
DAC A  
DAC B  
DAC C  
DAC D  
OUTB  
OUTA  
OUTC  
OUTD  
V
1
2
20  
19  
OUTB  
OUTC  
OUTD  
V
SS  
3
18 DD  
12-BIT  
SHIFT  
REGISTER  
INPUT  
REG B  
DAC  
REG B  
REFB  
REFC  
4
MAX509  
17  
16  
15  
14  
13  
12  
11  
REFA  
AGND  
N.C.  
REFD  
CS  
5
INPUT  
REG C  
6
DAC  
REG C  
N.C.  
SCLK  
DIN  
7
DGND  
LDAC  
8
INPUT  
REG D  
DAC  
REG D  
SR  
CONTROL  
9
DOUT  
CLR  
10  
REFD  
DIP/SO/SSOP  
SCLK  
REFC  
CS DIN  
Pin Configurations continued at end of data sheet.  
Microwire is a trademark of National Semiconductor. SPI and QSPI are trademarks of Motorola.  
________________________________________________________________ Maxim Integrated Products  
Functional Diagrams continued at end of data sheet.  
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800  
1234567...20

中文翻译

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MAX509BEAP 替代型号

型号 品牌 替代类型 描述 数据表
MAX509ACAP+ MAXIM

完全替代

 D/A Converter, 4 Func, Serial Input Loading, 6us Settling Time, PDSO20, SSOP-20

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