Datasheet > 电信电路 > ATM/SONET/SDH 集成电路> MAX3877

MAX3877

更新时间： 2024-02-07 22:19:25

品牌	Logo	应用领域
美信 - MAXIM		时钟
页数	文件大小	规格书
16页	551K
描述
2.5Gbps, +3.3V Clock and Data Retiming ICs with Vertical Threshold Adjust

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中文翻译

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技术参数
数据手册

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MAX3877 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	TFQFP,	针数：	32
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.81	Is Samacsys：	N
JESD-30 代码：	S-PQFP-G32	JESD-609代码：	e3
长度：	5 mm	湿度敏感等级：	1
功能数量：	1	端子数量：	32
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	TFQFP
封装形状：	SQUARE	封装形式：	FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	260	认证状态：	Not Qualified
座面最大高度：	1.2 mm	标称供电电压：	3.3 V
表面贴装：	YES	技术：	BIPOLAR
电信集成电路类型：	ATM/SONET/SDH CLOCK RECOVERY CIRCUIT	温度等级：	INDUSTRIAL
端子面层：	TIN	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	5 mm
Base Number Matches：	1

MAX3877 数据手册

2.5Gbps, +3.3V Clock and Data Retiming ICs

with Vertical Threshold Adjust

50mVp-p up to 1200mVp-p. For interfacing with PECL

signal levels, see Applications Information.

Detailed Description

The MAX3877/MAX3878 consist of a fully integrated

phase-locked loop (PLL), input amplifier, data retiming

block, and CML output buffer (MAX3877) or PECL out-

put buffer (MAX3878). The PLL consists of a phase/fre-

quency detector (PFD), a loop filter, and a

voltage-controlled oscillator (VCO). Figure 5 shows the

functional diagram.

Phase/Frequency Detector

The phase detector incorporated in the MAX3877 and

MAX3878 produces a voltage proportional to the phase

difference between the incoming data and the internal

clock. Because of its feedback nature, the PLL drives

the error voltage to zero, aligning the recovered clock

to the center of the incoming data eye for retiming.

This device is designed to deliver the best combination

of jitter performance and power dissipation by using a

fully differential signal architecture and low-noise

design techniques.

The digital frequency detector (FD) aids frequency

acquisition during startup conditions. The frequency

difference between the received data and the VCO

clock is derived by sampling the in-phase and quadra-

ture VCO output on the rising edges of the data input

signal. The FD drives the VCO until the frequency dif-

ference is reduced to zero. Once frequency acquisition

is complete, the FD returns to a neutral state. False

locking is completely eliminated by this digital frequen-

cy detector.

SDI Input Amplifier

The SDI input amplifier accepts 2.488Gbps NRZ data

with differential input swing from 10mVp-p up to

1200mVp-p. The bit error rate is better than 1 10^-10for

input signals as small as 4mVp-p, though the jitter toler-

ance performance will be degraded. This amplifier

allows for adjustment of the input threshold level. For

interfacing with PECL signal levels, see Applications

Information, or refer to Applications Note HFAN 1.0,

Interfacing Between CML, PECL, and LVDS.

While in holdover mode, a Type 4 phase/frequency

detector (PFD) is implemented to track the 155MHz ref-

erence clock signal. This PFD compares the incoming

155MHz reference clock with the divided down VCO

clock. The LREF input is used to enable holdover mode

(see Applications Information).

SLBI Input Amplifier

The SLBI input amplifier accepts either 2.488Gbps

loopback data or a 155MHz reference clock. This

amplifier accepts data with differential input swing from

FIL+ FIL-

GND

CPWD+ CPWD-

THRESHOLD

ADJUST

THADJ

SDO+

AMP

SDO-

SDI-

SDI+

AMP

DC-OFFSET/

PWD

CANCELLATION

PHASE &

FREQUENCY

DETECTOR

SCLKO+

SCLKO-

LOOP

MUX

VCO

FILTER

SLBI-

SLBI+

/16

PHADJ

SIS

LREF

LOSS OF

SIGNAL

DETECTOR

LOL

LOS

LOL

LOS

Figure 5. Functional Diagram

_______________________________________________________________________________________

1...6 7 8910 11 12...16

中文翻译

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与MAX3877相关器件

型号	品牌	获取价格	描述	数据表
MAX3877E/D	MAXIM	获取价格	Clock Recovery Circuit, 1-Func, Bipolar, 2.311 X 2.286 MM, DIE-42
MAX3877EHJ	MAXIM	获取价格	2.5Gbps, +3.3V Clock and Data Retiming ICs with Vertical Threshold Adjust
MAX3877EHJ+	MAXIM	获取价格	Clock Recovery Circuit, 1-Func, Bipolar, PQFP32, 5 X 5 MM, 1 MM HEIGHT, EXPOSED PAD, TQFP-
MAX3877EHJ+T	MAXIM	获取价格	Clock Recovery Circuit, 1-Func, Bipolar, PQFP32, 5 X 5 MM, 1 MM HEIGHT, EXPOSED PAD, TQFP-
MAX3877EHJ-T	MAXIM	获取价格	暂无描述
MAX3877EVKIT	MAXIM	获取价格	Evaluation Kits for the MAX3877/MAX3878
MAX3878	MAXIM	获取价格	2.5Gbps.+3.3V Clock and Data Retiming ICs with Vertical Threshold Adjust
MAX3878EHJ	MAXIM	获取价格	2.5Gbps, +3.3V Clock and Data Retiming ICs with Vertical Threshold Adjust
MAX3878EHJ-T	MAXIM	获取价格	Clock Recovery Circuit, 1-Func, Bipolar, PQFP32, 5 X 5 MM, 1 MM HEIGHT, EXPOSED PAD, TQFP-
MAX3878EVKIT	MAXIM	获取价格	Evaluation Kits for the MAX3877/MAX3878

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