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MAX3877

更新时间： 2024-02-22 17:54:36

品牌	Logo	应用领域
美信 - MAXIM		时钟
页数	文件大小	规格书
16页	551K
描述
2.5Gbps, +3.3V Clock and Data Retiming ICs with Vertical Threshold Adjust

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中文翻译

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技术参数
数据手册

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MAX3877 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	TFQFP,	针数：	32
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.81	Is Samacsys：	N
JESD-30 代码：	S-PQFP-G32	JESD-609代码：	e3
长度：	5 mm	湿度敏感等级：	1
功能数量：	1	端子数量：	32
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	TFQFP
封装形状：	SQUARE	封装形式：	FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	260	认证状态：	Not Qualified
座面最大高度：	1.2 mm	标称供电电压：	3.3 V
表面贴装：	YES	技术：	BIPOLAR
电信集成电路类型：	ATM/SONET/SDH CLOCK RECOVERY CIRCUIT	温度等级：	INDUSTRIAL
端子面层：	TIN	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	5 mm
Base Number Matches：	1

MAX3877 数据手册

2.5Gbps, +3.3V Clock and Data Retiming ICs

with Vertical Threshold Adjust

The BER is better than 1 10^-10for input signals

greater than 4mVp-p. At 5mVp-p, jitter tolerance will be

degraded, but will still be above the SDH/SONET

requirement. The user can make a trade-off between jit-

ter tolerance and input sensitivity according to the spe-

cific application. Refer to Typical Operating

Characteristics for Jitter Tolerance and BER vs. Input

Amplitude.

50Ω

0.1µF

25Ω

Applications Information

SDI+

SDI-

Holdover Mode

When in holdover mode, the MAX3877/MAX3878 can

lock to an external reference clock to maintain a valid

clock output in the absence of input data. When LREF is

high, the PLL locks to an external 155.52MHz reference

clock, which is applied to the SLBI inputs. To enter

holdover mode automatically when there are no transi-

tions to the SDI inputs, LOS can be directly tied to LREF.

By maintaining frequency lock, the time required to re-

acquire lock is reduced.

PECL

LEVELS

100Ω

MAX3877

System Loopback

The system loopback input may be used as an auxiliary

input for system loopback testing or as input for an exter-

nal 155.52MHz reference clock. When used as a loop-

back test, the user can connect a serializer output in a

transceiver directly to the SLBI inputs for system diag-

nostics. Using an external reference clock can maintain

PLL frequency lock in the absence of transitions on the

SDI inputs.

Figure 10. Interfacing with PECL Levels

50Ω

Consecutive Identical Digits (CID)

SDO+

SDO-

The MAX3877/MAX3878 have low frequency drift in the

absence of data transitions. As a result, long runs of con-

secutive zeros and ones can be tolerated while maintain-

ing a BER better than 1 10^-10. The CID tolerance is

tested using a 2¹³- 1PRBS, substituting a long run of

zeros to simulate the worst case. A CID tolerance of

2000 bits is typical.

MAX3877

The VCO frequency after 4096 bits (approximately 1.6µs)

may be estimated by using the VCO drift rate:

Figure 11. CML Outputs









6.2kHz

µs

f = 2.488GHz

1.65µs ×





Jitter Tolerance and Input Sensitivity

Trade-Offs

= 2.488GHz 10.21kHz = 2.488GHz

4.1ppm

When the received data amplitude is higher than

10mVp-p, the MAX3877/MAX3878 provide a typical jit-

ter tolerance of 0.64UI at jitter frequencies greater than

10MHz. The SDH/SONET jitter tolerance specification is

0.15UI, leaving a jitter allowance of 0.49UI for receiver

preamplifier and postamplifier design.

Exposed Pad (EP) Package

The exposed pad, 32-pin TQFP incorporates features

that provide a very low thermal-resistance path for heat

removal from the IC. The pad is electrical ground on the

MAX3877/MAX3878 and should be soldered to the cir-

cuit board for proper thermal and electrical performance.

±2 ______________________________________________________________________________________

1...9 10 111213 14 15 16

中文翻译

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与MAX3877相关器件

型号	品牌	获取价格	描述	数据表
MAX3877E/D	MAXIM	获取价格	Clock Recovery Circuit, 1-Func, Bipolar, 2.311 X 2.286 MM, DIE-42
MAX3877EHJ	MAXIM	获取价格	2.5Gbps, +3.3V Clock and Data Retiming ICs with Vertical Threshold Adjust
MAX3877EHJ+	MAXIM	获取价格	Clock Recovery Circuit, 1-Func, Bipolar, PQFP32, 5 X 5 MM, 1 MM HEIGHT, EXPOSED PAD, TQFP-
MAX3877EHJ+T	MAXIM	获取价格	Clock Recovery Circuit, 1-Func, Bipolar, PQFP32, 5 X 5 MM, 1 MM HEIGHT, EXPOSED PAD, TQFP-
MAX3877EHJ-T	MAXIM	获取价格	暂无描述
MAX3877EVKIT	MAXIM	获取价格	Evaluation Kits for the MAX3877/MAX3878
MAX3878	MAXIM	获取价格	2.5Gbps.+3.3V Clock and Data Retiming ICs with Vertical Threshold Adjust
MAX3878EHJ	MAXIM	获取价格	2.5Gbps, +3.3V Clock and Data Retiming ICs with Vertical Threshold Adjust
MAX3878EHJ-T	MAXIM	获取价格	Clock Recovery Circuit, 1-Func, Bipolar, PQFP32, 5 X 5 MM, 1 MM HEIGHT, EXPOSED PAD, TQFP-
MAX3878EVKIT	MAXIM	获取价格	Evaluation Kits for the MAX3877/MAX3878

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