Datasheet > 电信电路 > ATM/SONET/SDH 集成电路> MAX3831UCB-T

MAX3831UCB-T

更新时间： 2024-01-27 16:55:28

品牌	Logo	应用领域
美信 - MAXIM		时钟发生器
页数	文件大小	规格书
16页	285K
描述
ATM/SONET/SDH Mux/Demux, 1-Func, PQFP64, 10 X 10 MM, 1 MM HEIGHT, MO-136AJ, TQFP-64

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

MAX3831UCB-T 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	HTFQFP,	针数：	64
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.9
JESD-30 代码：	S-PQFP-G64	JESD-609代码：	e0
长度：	10 mm	湿度敏感等级：	3
功能数量：	1	端子数量：	64
最高工作温度：	85 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	HTFQFP
封装形状：	SQUARE	封装形式：	FLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	245	认证状态：	Not Qualified
座面最大高度：	1.2 mm	标称供电电压：	3.3 V
表面贴装：	YES	电信集成电路类型：	ATM/SONET/SDH MUX/DEMUX
温度等级：	OTHER	端子面层：	TIN LEAD
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	10 mm	Base Number Matches：	1

MAX3831UCB-T 数据手册

+3.3V, 2.5Gbps, SDH/SONET, 4-Channel

Interconnect Mux/Demux ICs with Clock Generator

clocꢁ cycle between each channel. In this test mode, ser-

ial data is internally looped bacꢁ to the demux. All frame

detect logic is exercised using this mode. The CML

inputs (SDI± and SCLKI±) and LVDS inputs (PDI_±) are

ignored in this mode. After the BIST mode is enabled, the

loss-of-frame flag LOF goes high, indicating that the self-

test has passed. In normal operation, TEST is left open

(internally pulled high), disabling the pattern generator

and accepting data from the parallel input channels.

50Ω

SDO+ SDI+

SDO- SDI-

Test Loopbacks

Two additional test loopbacꢁs are provided: parallel

system loopbacꢁ and serial line loopbacꢁ.

Parallel System Loopback

In parallel system loopbacꢁ, four 622Mbps parallel

input channels are phase aligned by an associated 10-

bit elastic store and routed to the output LVDS buffers.

This loopbacꢁ is controlled by setting PLBEN low.

Normal data transmission is resumed when PLBEN

goes high (internally pulled high).

MAX3831

MAX3832

MAX3876

Serial Line Loopback

Serial line loopbacꢁ is used for testing the performance

of the optical transceiver and the transmission linꢁ. The

received 2.488Gbps data stream is routed to the trans-

mit CML output buffer. Line loopbacꢁ is enabled when

LBEN is asserted low. When LBEN is left open (internally

pulled high), normal serial-data transmission resumes.

Figure 7. CML-to-CML Interface

__________Applications Information

Low-Voltage Differential

Signal Inputs/Outputs

The MAX3831/MAX3832 have LVDS inputs and outputs

for interfacing with high-speed digital circuitry. All LVDS

inputs and outputs are compatible with the IEEE-1ꢀ96.3

LVDS specification. This technology uses 2ꢀ0mV to

400mV differential low-voltage amplitudes to achieve

fast transition times, minimize power dissipation, and

improve noise immunity.

LVDS Parallel Interface

The MAX3831 parallel interface includes four OC-12

data inputs, a 1ꢀꢀMHz reference clocꢁ input, four

622Mbps parallel-data outputs, and a 622MHz parallel-

clocꢁ output (MAX3832, f

= 1ꢀꢀMHz). All parallel

PCLKO

inputs and outputs are LVDS compatible to minimize

power dissipation, speed transition time, and improve

noise immunity. The 1ꢀꢀMHz input signal at RCLKI

requires a duty cycle between 40ꢂ and 60ꢂ.

For proper operation, the parallel clocꢁ and data LVDS

outputs (PCLKO+, PCLKO-, PDO_+, PDO_-) require

100Ω differential DC termination between the inverting

and noninverting outputs. Do not terminate these out-

puts to ground. The parallel-data LVDS inputs (PDI_+,

PDI_-) are internally terminated with 100Ω differential

input resistance and therefore do not require external

termination.

The LVDS outputs go into a high-impedance state when

TRIEN is forced low. This simplifies system checꢁs by

allowing vectors to be forced on the LVDS outputs.

CML Serial Interface

The MAX3831/MAX3832 provide a 2.488Gbps serial-

data stream to a driver and accept 2.488Gbps serial

data and a 2.488GHz clocꢁ signal from an external

clocꢁ and data recovery device (MAX38±6). The high-

speed interface is CML compatible, resulting in lower

system power dissipation and excellent performance

(Figure ±).

Interfacing with PECL/ECL

Input Levels

When interfacing with differential PECL input levels, it is

important to attenuate the signal while still maintaining

ꢀ0Ω termination (Figures 8 and 9). Observe the com-

mon-mode input voltage specifications. AC-coupling is

required if a V

other than 3.3V is used to maintain the

input common-mode level (Figure 8).

10 ______________________________________________________________________________________

1...7 8 91011 12 13...16

中文翻译

下载PDF

与MAX3831UCB-T相关器件

型号	品牌	获取价格	描述	数据表
MAX3831UCB-TD	MAXIM	获取价格	ATM/SONET/SDH Mux/Demux, 1-Func, PQFP64, 10 X 10 MM, 1 MM HEIGHT, MO-136AJ, TQFP-64
MAX3832	MAXIM	获取价格	2x4-Channel.Simultaneous-Sampling.14-Bit DAS[MAX125/MAX126/MAX125/MAX126/MAX125/MAX126/MAX
MAX3832EVKIT	MAXIM	获取价格	Evaluation Kit for the MAX3831/MAX3832
MAX3832UCB	MAXIM	获取价格	+3.3V, 2.5Gbps, SDH/SONET, 4-Channel Interconnect Mux/Demux ICs with Clock Generator
MAX3832UCB-T	MAXIM	获取价格	Mux/Demux, 1-Func, PQFP64, 10 X 10 MM, 1 MM HEIGHT, MO-136AJ, TQFP-64
MAX383C/D	MAXIM	获取价格	Precision, Low-Voltage Analog Switches
MAX383CPE	MAXIM	获取价格	Precision, Low-Voltage Analog Switches
MAX383CPE+	MAXIM	获取价格	SPDT, 2 Func, 1 Channel, CMOS, PDIP16, 0.300 INCH, PLASTIC, DIP-16
MAX383CSE	MAXIM	获取价格	Precision, Low-Voltage Analog Switches
MAX383CSE+	MAXIM	获取价格	SPDT, 2 Func, 1 Channel, CMOS, PDSO16, 0.150 INCH, SO-16

与MAX3831UCB-T相关文章

压敏电阻器在直流电路中的过压保护应用探讨
2024-06-07

2
电感耐压值及其与电感大小的关系
2024-06-07

5
CNY17F光耦合器：特性、应用、封装、引脚功能及替换型号解析
2024-06-07

4
DS1307资料解析：特性、引脚说明、替代推荐
2024-06-07

3

产品中心

服务支持

精选活动

关于我们

帮助中心

MAX3831UCB-T

MAX3831UCB-T 技术参数

MAX3831UCB-T 数据手册

与MAX3831UCB-T相关器件

与MAX3831UCB-T相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

MAX3831UCB-T

MAX3831UCB-T 技术参数

MAX3831UCB-T 数据手册

与MAX3831UCB-T相关器件

与MAX3831UCB-T相关文章

您还可以找

您在本页遇到什么问题？