+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
Pin Description (continued)
PIN
NAMꢀ
FUNCTION
Elastic Store Reset. The elastic buffer is centered on a rising edge of RSETES, maximizing
the elastic store range. Data must be present for 10µs before applying a pulse of at least
10ns. An internal 1ꢀꢁΩ pull-up resistor pulls RSETES high for normal operation.
ꢀ8
RSETES
61
62
FIL-
Negative PLL Filter Capacitor Input. Connect a 0.33µF capacitor between FIL+ and FIL-.
Positive PLL Filter Capacitor Input. Connect a 0.33µF capacitor between FIL+ and FIL-.
FIL+
Ground. This must be soldered to a circuit board for proper thermal performance (see
Package Information).
EP
Exposed Paddle
Due to the inherent uncertainty of the data transitions
_______________Detailed Description
between the parallel-data inputs there is no bit or frame
alignment between these inputs. However, the demux
ensures proper channel assignment is maintained.
The MAX3831/MAX3832 use a 4:1 mux and 1:4 demux
with an elastic store buffer to simplify SDH/SONET
interconnect I/O routing. The 622Mbps low-voltage dif-
ferential signal (LVDS) parallel inputs pass through the
10-bit elastic store buffer, which accommodates ±±.ꢀns
sꢁew on any single input relative to the 1ꢀꢀMHz refer-
ence clocꢁ input RCLKI. This reference clocꢁ is
required to synthesize the internal 2.488GHz clocꢁ
used to drive the elastic store and 4:1 multiplexer. All
TTL and LVDS outputs can be placed in a high-imped-
ance state. See Figure 4 for a functional diagram.
Bit-Interleaved Multiplexer/
Demultiplexer
The MAX3831/MAX3832 use a bit interleave/deinterleave
mux/demux. To guarantee channel assignment, one of
the four channels is inverted before multiplexing to pro-
vide a reference for the frame detector during demulti-
plexing. After demultiplexing, the same channel is
inverted bacꢁ to the original data format.
The 4:1 mux bit-interleaves the parallel data, providing
a 2.488Gbps CML serial output to the optical or electri-
cal driver. The CML serial input receives the
2.488Gbps data, the demux deinterleaves it to
622Mbps and sends the data to the frame detector.
The frame detector monitors one 622Mbps channel and
rolls the demux into the proper channel assignment.
The MAX3831/MAX3832 include high-speed, built-in
self-test (BIST), which also allows testing of the
622Mbps parallel-system loopbacꢁ and the 2.488Gbps
line loopbacꢁ.
Frame Detector
After a 2.ꢀGbps serial data is bit deinterleaved into four
622Mbps channels, an SDH/SONET frame detector
monitors the fourth channel, looꢁing for the 32-bit pat-
tern (A1A1A2A2) in the OC-12 header. To maintain cor-
rect channel assignment, the demux outputs rotate until
this 32-bit overhead pattern is reliably detected. A loss-
of-frame output, LOF, indicates when the received data
is in or out of frame. When LOF goes high, the frame
pattern is detected and the demux outputs are correct-
ly assigned. When LOF is low, the frame detection cir-
cuitry is searching for the correct frame. A RSETFR
(TTL, active low) is included to reset the frame detector
when necessary.
Elastic Store Buffer
Each parallel-data input, PDI1 to PDI4, passes through
its respective 10-bit elastic store buffer. Following an
elastic store reset, this buffer accommodates ±±.ꢀns of
sꢁew on any input relative to the 1ꢀꢀMHz reference
clocꢁ. Figure ꢀ illustrates the elastic store buffer rela-
tionship with RCLKI. The Elastic Store Range graph in
the Typical Operating Characteristics shows the
amount of data sꢁew tolerated.
The frame detector uses an algorithm to detect an in-
frame condition and a loss-of-frame condition; this algo-
rithm is implemented to meet the SONET in-frame and
false-frame specs. The frame_search state will occur
upon start-up or reset. In this state, the frame detector
scans through the incoming serial data searching for the
framing pattern in the channel 4 output of the demux.
While in this state, if the framing pattern is not found
within 2ꢀ0µs, the demux channels are shifted (rolled)
and the frame search continues (Figure 6).
Following a 10µs power-up period, the locations of the
individual data-channel bit transitions are acquired,
guaranteeing data preservation. The output of this
blocꢁ passes directly into the 4:1 mux. After power-up,
the elastic store buffer must be reset by applying a low
pulse on RSETES for at least 10ns.
In-frame will be declared if two consecutive framing
patterns are found at the correct byte locations within
the SONET frame (9±20 bytes). If this pattern is not pre-
_______________________________________________________________________________________________________
±
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