19-3781; Rev 0; 8/05
USB Peripheral Controller
with SPI Interface
General Description
Features
The MAX3420E contains the digital logic and analog
circuitry necessary to implement a full-speed USB
peripheral compliant to USB specification rev 2.0. A
built-in full-speed transceiver features ±±15k ESꢀ pro-
tection and programmable USB connect and discon-
nect. An internal SIE (serial-interface engine) handles
low-level USB protocol details such as error chec5ing
and bus retries. The MAX3420E operates using a regis-
ter set accessed by an SPI interface that operates up to
26MHz. Any SPI master (microprocessor, ASIC, ꢀSP,
etc.) can add USB functionality using the simple 3- or
4-wire SPI interface.
♦ Microprocessor-Independent USB Solution
♦ Complies with USB Specification Revision 2.0
(Full-Speed Operation)
♦ Integrated Full-Speed USB Transceiver
♦ Firmware/Hardware Control of an Internal D+
Pullup Resistor
♦ Programmable 3- or 4-Wire 26MHz SPI Interface
♦ Level Translators and V Input Allow Independent
L
System Interface Voltage
Internal level translators allow the SPI interface to run at
a system voltage between ±.7±k and 3.6k. USB timed
operations are done inside the MAX3420E with inter-
rupts provided at completion so an SPI master does not
need timers to meet USB timing requirements. The
MAX3420E includes four general-purpose inputs and
outputs so any microprocessor that uses I/O pins to
implement the SPI interface can reclaim the I/O pins
and gain additional ones.
♦ Internal Comparator Detects V
Self-Powered Applications
♦ ESD Protection on D+, D-, and VBCOMP
for
BUS
♦ Interrupt Output Pin (Level or Programmable
Edge) Allows Polled or Interrupt-Driven SPI
Interface
♦ Intelligent USB Serial Interface Engine (SIE)
Automatically Handles USB Flow Control and
Double Buffering
The MAX3420E operates over the extended -40°C to
+81°C temperature range and is available in a 32-pin
TQFP pac5age (7mm x 7mm) and a space-saving 24-
pin TQFN pac5age (4mm x 4mm).
Handles Low-Level USB Signaling Details
Contains Timers for USB Time-Sensitive
Operations So SPI Master Does Not Need to
Time Events
Applications
Cell Phones
PLCs
♦ Built-In Endpoint FIFOs:
PC Peripherals
Set-Top Boxes
PꢀAs
EP0: CONTROL (64 Bytes)
Microprocessors and
ꢀSPs
EP1: OUT, Bulk or Interrupt, 2 x 64 Bytes
(Double-Buffered)
MP3 Players
Instrumentation
Custom USB ꢀevices
Cameras
EP2: IN, Bulk or Interrupt, 2 x 64 Bytes
(Double-Buffered)
ꢀes5top Routers
EP3: IN, Bulk or Interrupt (64 Bytes)
♦ Double-Buffered Data Endpoints Increase
Throughput by Allowing the SPI Master to
Transfer Data Concurrently with USB Transfers
Over the Same Endpoint
Ordering Information
PIN-
PACKAGE
CODE
PART
TEMP RANGE
PACKAGE
♦ SETUP Data Has Its Own 8-Byte FIFO, Simplifying
Firmware
32 TQFP
MAX3420EECJ -40°C to +81°C 7mm x 7mm x
±.4mm
C32-±
♦ Four General-Purpose Inputs and Four General-
Purpose Outputs
24 TQFN
MAX3420EETG* -40°C to +81°C 4mm x 4mm x
0.8mm
♦ Space-Saving TQFP and TQFN Packages
T2444-4
*Future product—contact factory for availability.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.