Datasheet > MAX24605

MAX24605

更新时间： 2024-11-17 14:54:11

品牌	Logo	应用领域
美国微芯 - MICROCHIP		/
页数	文件大小	规格书
116页	1593K
描述
The MAX24605 is a flexible, high-performance clock multiplier and jitter attenuator ICs that inclu

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MAX24605 数据手册

Data Sheet

April 2019

MAX24605, MAX24610

5- or 10-Output Any-to-Any Clock Multiplier /

Jitter Attenuator ICs

General Description

Features



Input Clocks

The MAX24605 and MAX24610 are flexible, high-

performance clock multiplier and jitter attenuator ICs

that include a DPLL and two independent APLLs. When

locked to one of two input clock signals, the device

performs any-to-any frequency conversion. From any

input clock frequency 2kHz to 750MHz the device can

produce frequency-locked APLL output frequencies up

to 750MHz and as many as 10 output clock signals that

are integer divisors of the APLL frequencies. Input jitter

can be attenuated by an internal low-bandwidth DPLL.

The DPLL also provides glitchless switching between

input clocks and numerically controlled oscillator

capability. Input switching can be manual or automatic.

Using only a low-cost crystal or oscillator, the device

can also serve as a frequency synthesizer IC. Output

jitter is typically 0.18 to 0.3ps RMS for an APLL-only

integer multiply and 0.25 to 0.4ps RMS for APLL-only

fractional multiply or DPLL+APLL operation.



One Crystal Input

Two Differential or CMOS/TTL Inputs

Differential to 750MHz, CMOS/TTL to 160MHz

Continuous Input Clock Quality Monitoring

Automatic or Manual Clock Selection

Glitchless Reference Switching



Low-Bandwidth DPLL



Programmable Bandwidth, 4Hz to 400Hz

Attenuates Input Jitter up to Several UI

Manual Phase Adjustment

Two APLLs Plus 5 or 10 Output Clocks



APLLs Perform High Resolution Fractional-N

Clock Multiplication



Any Output Frequency from <1Hz to 750MHz

Each Output Has an Independent Divider

Applications

Jitter attenuation, frequency conversion and frequency

synthesis applications in a wide variety of equipment

types

Output Jitter Typically 0.18 to 0.3ps RMS for

APLL-Only Integer Multiply and 0.25 to 0.4ps

RMS for Other Modes (12kHz to 20MHz)



Outputs are CML or 2xCMOS, Can Interface to

LVDS, LVPECL, HSTL, SSTL and HCSL

Ordering Information

CMOS Output Voltage from 1.5V to 3.3V

TEMP

PIN-

PART

OUTPUTS

RANGE

PACKAGE



General Features

MAX24605EXG2

MAX24610EXG2

-40 to +85

81-CSBGA



Automatic Self-Configuration at Power-Up

from External EEPROM Memory

Suffix 2 denotes a lead(Pb)-free/RoHS-compliant package.

Uses External Crystal, Oscillator or Clock

Signal As Master Clock

Block Diagram appears on page 6.

Internal Compensation for Local Oscillator

Frequency Error



SPI Processor Interface

1.8V + 3.3V Operation (5V Tolerant)

-40 to +85C Operating Temp. Range

10mm x 10mm CSBGA Package

12 3 4 5 6 7...116

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与MAX24605相关器件

型号	品牌	获取价格	描述	数据表
MAX24605EXG+	MICROSEMI	获取价格	Telecom Circuit, 1-Func, PBGA81, CSBGA-81
MAX2460EAI	MAXIM	获取价格	900MHz Image-Reject Transceivers
MAX2460EAI	ROCHESTER	获取价格	TELECOM, CELLULAR, RF AND BASEBAND CIRCUIT, PDSO28, 5.30 MM, MO-150, SSOP-28
MAX2460EAI+	MAXIM	获取价格	RF and Baseband Circuit, PDSO28, 5.30 MM, MO-150, SSOP-28
MAX2460EAI+	ROCHESTER	获取价格	TELECOM, CELLULAR, RF AND BASEBAND CIRCUIT, PDSO28, 5.30 MM, MO-150, SSOP-28
MAX2460EAI+T	MAXIM	获取价格	暂无描述
MAX2460EAI-T	MAXIM	获取价格	RF and Baseband Circuit, PDSO28, 5.30 MM, MO-150, SSOP-28
MAX24610EXG+	MICROSEMI	获取价格	Telecom Circuit, 1-Func, PBGA81, CSBGA-81
MAX2463	MAXIM	获取价格	Evaluation Kit for the MAX713 (Switching Applications)[MAX713SWEVKIT ]
MAX2463EAI	MAXIM	获取价格	900MHz Image-Reject Transceivers

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