5秒后页面跳转
MAX24405EXG+ PDF预览

MAX24405EXG+

更新时间: 2024-11-15 19:43:27
品牌 Logo 应用领域
美高森美 - MICROSEMI 时钟外围集成电路晶体
页数 文件大小 规格书
4页 184K
描述
Clock Generator, 750MHz, CMOS, PBGA81, CSBGA-81

MAX24405EXG+ 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:LBGA,Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.77其他特性:IT ALSO OPERATES AT 50MHZ AND 25MHZ CRYSTAL FREQUENCY
JESD-30 代码:S-PBGA-B81长度:10 mm
端子数量:81最高工作温度:85 °C
最低工作温度:-40 °C最大输出时钟频率:750 MHz
封装主体材料:PLASTIC/EPOXY封装代码:LBGA
封装形状:SQUARE封装形式:GRID ARRAY, LOW PROFILE
峰值回流温度(摄氏度):NOT SPECIFIED主时钟/晶体标称频率:51.2 MHz
座面最大高度:1.47 mm最大供电电压:1.89 V
最小供电电压:1.71 V标称供电电压:1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:10 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

MAX24405EXG+ 数据手册

 浏览型号MAX24405EXG+的Datasheet PDF文件第2页浏览型号MAX24405EXG+的Datasheet PDF文件第3页浏览型号MAX24405EXG+的Datasheet PDF文件第4页 
Short Form Data Sheet  
June 2012  
MAX24405, MAX24410  
5 or 10 Output Any-Rate Clock Multipliers  
General Description  
Features  
Input Clocks  
The MAX24405 and MAX24410 are flexible, high-  
performance clock multiplier/synthesizer ICs with two  
independent APLLs. Each APLL performs any-to-any  
frequency conversion. From any input clock frequency  
9.72MHz to 750MHz these devices can produce  
frequency-locked APLL output frequencies up to  
750MHz and as many as 10 differential output clock  
signals that are integer divisors of the APLL  
frequencies. Output jitter is typically 0.35 to 0.5ps RMS  
(12kHz to 20MHz) on all outputs and can be as low as  
0.24ps RMS. Each device can configure itself from an  
external EEPROM so that clock signals are available  
immediately after power-up or reset.  
One Crystal or CMOS Input  
Three Differential or CMOS Inputs  
Differential to 750MHz, CMOS to 125MHz  
Clock Selection By Pin or Register Control  
Two APLLs Plus 5 or 10 Output Clocks  
APLLs Perform High Resolution Fractional-N  
Clock Multiplication  
Any Output Frequency from <1Hz to 750MHz  
Each Output Has an Independent Divider  
Output Jitter 0.35 to 0.5ps RMS Typical on All  
Outputs, Can Be As Low As 0.24ps RMS  
Outputs are CML or 2xCMOS, Can Interface to  
LVDS, LVPECL, HSTL, SSTL and HCSL  
CMOS Output Voltage from 1.5V to 3.3V  
Applications  
Frequency Conversion and Synthesis Applications in a  
Wide Variety of Equipment Types  
General Features  
Automatic Self-Configuration at Power-Up  
from External EEPROM Memory  
SPI™ Processor Interface  
1.8V + 3.3V Operation (5V Tolerant)  
-40 to +85°C Operating Temp. Range  
Ordering Information  
PART  
OUTPUTS  
PIN-PACKAGE  
MAX24405EXG+  
MAX24410EXG+  
5
81-CSBGA (10mm)2  
81-CSBGA (10mm)2  
10  
Block Diagram  
DIV1  
DIV2  
DIV3  
DIV4  
DIV5  
DIV6  
DIV7  
DIV8  
DIV9  
OC1POS/NEG  
OC2POS/NEG  
OC3POS/NEG  
OC4POS/NEG  
OC5POS/NEG  
OC6POS/NEG  
OC7POS/NEG  
OC8POS/NEG  
OC9POS/NEG  
OC10POS/NEG  
APLL1  
3.7-4.2GHz,  
Sub-ps jitter,  
Fractional-N  
A
B
MAX24410 only  
MAX24410 only  
IC1POS/NEG  
APLL2  
3.7-4.2GHz,  
Sub-ps jitter,  
Fractional-N  
IC2POS/NEG  
IC3POS/NEG  
XIN  
C
D
XO  
XOUT  
DIV10  
Processor SPI Interface  
EEPROM SPI Interface  
and HW Control and Status Pins  
JTAG  
1

与MAX24405EXG+相关器件

型号 品牌 获取价格 描述 数据表
MAX2440EAI MAXIM

获取价格

900MHz Image-Reject Receivers
MAX2440EAI+T MAXIM

获取价格

暂无描述
MAX2440EAI-T MAXIM

获取价格

RF and Baseband Circuit, PDSO28, 5.30 MM, 6.50 MM PITCH, SSOP-28
MAX2441 MAXIM

获取价格

900MHz Image Reject Receivers
MAX24410EXG+ MICROSEMI

获取价格

Clock Generator, 750MHz, CMOS, PBGA81, CSBGA-81
MAX2441EAI MAXIM

获取价格

900MHz Image-Reject Receivers
MAX2441EAI+ MAXIM

获取价格

RF and Baseband Circuit, PDSO28, 5.30 MM, 6.50 MM PITCH, SSOP-28
MAX2442 MAXIM

获取价格

900MHz Image Reject Receivers
MAX2442EAI MAXIM

获取价格

900MHz Image-Reject Receivers
MAX2442EAI+ MAXIM

获取价格

RF and Baseband Circuit, PDSO28, 5.30 MM, 6.50 MM PITCH, SSOP-28