Datasheet > MAX24310EXG+

MAX24310EXG+

更新时间： 2024-11-15 15:40:39

品牌	Logo	应用领域
美高森美 - MICROSEMI		ATM 异步传输模式电信电信集成电路
页数	文件大小	规格书
4页	298K
描述
Support Circuit, 1-Func, PBGA81, 10 X 10 MM, ROHS COMPLIANT, CSBGA-81

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技术参数
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MAX24310EXG+ 技术参数

是否Rohs认证：	符合	生命周期：	Active
零件包装代码：	BGA	包装说明：	LBGA,
针数：	81	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.8
JESD-30 代码：	S-PBGA-B81	长度：	10 mm
功能数量：	1	端子数量：	81
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	LBGA
封装形状：	SQUARE	封装形式：	GRID ARRAY, LOW PROFILE
峰值回流温度（摄氏度）：	260	座面最大高度：	1.47 mm
标称供电电压：	1.8 V	表面贴装：	YES
电信集成电路类型：	ATM/SONET/SDH SUPPORT CIRCUIT	温度等级：	INDUSTRIAL
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	30
宽度：	10 mm	Base Number Matches：	1

MAX24310EXG+ 数据手册

Short Form Data Sheet

August 2014

MAX24305, MAX24310

5- or 10-Output Any-to-Any Timing ICs

with Internal EEPROM

General Description

Features

♦

Input Clocks

The MAX24305 and MAX24310 are flexible, high-

performance timing and clock synthesizer ICs that

include a DPLL and two independent APLLs. When

locked to one of two input clock signals, the device

performs any-to-any frequency conversion. From any

input clock frequency 1Hz to 750MHz the device can

produce frequency-locked APLL output frequencies up

to 750MHz and as many as 10 output clock signals that

are integer divisors of the APLL frequencies. Input jitter

can be attenuated by an internal low-bandwidth DPLL.

The DPLL also provides truly hitless switching between

input clocks and a high-resolution holdover capability.

Input switching can be manual or automatic. Using only

a low-cost crystal or oscillator, the device can also serve

as a frequency synthesizer IC. Output jitter is typically

0.18 to 0.3ps RMS for an APLL-only integer multiply

and 0.25 to 0.4ps RMS for APLL-only fractional multiply

or DPLL+APLL operation.

♦

One Crystal Input

Two Differential or CMOS/TTL Inputs

Differential to 750MHz, CMOS/TTL to 160MHz

Continuous Input Clock Quality Monitoring

Automatic or Manual Clock Selection

Hitless Reference Switching on Loss of Input

♦

Low-Bandwidth DPLL

♦

Programmable Bandwidth, 0.5mHz to 400Hz

Attenuates Jitter up to Several UI

Free-Run or Holdover on Loss of All Inputs

Hitless Reference Switching on Loss of Input

Manual Phase Adjustment

Two APLLs Plus 5 or 10 Output Clocks

For telecom systems, the device has all required

features and functions to serve as a central timing

function or as a line card timing IC. With a suitable

oscillator the device meets the requirements of Stratum

2, 3E, 3, 4E, and 4; G.812 Types I to IV; G.813; and

G.8262.

♦

APLLs Perform High Resolution Fractional-N

Clock Multiplication

♦

Any Output Frequency from <1Hz to 750MHz

Each Output Has an Independent Divider

Output Jitter Typically 0.18 to 0.3ps RMS for

APLL-Only Integer Multiply and 0.25 to 0.4ps

RMS for Other Modes (12kHz to 20MHz)

Applications

Frequency Conversion and Synthesis Applications in a

Wide Variety of Equipment Types

♦

Outputs are CML or 2xCMOS, Can Interface to

LVDS, LVPECL, HSTL, SSTL and HCSL

Telecom Timing Cards or Line Cards for SONET/SDH,

Synchronous Ethernet and/or OTN

CMOS Output Voltage from 1.5V to 3.3V

♦

General Features

♦

Suitable Line Card IC or Timing Card IC for

Stratum 2/3E/3/4E/4, SMC, SEC/EEC, or SSU

Ordering Information

TEMP

PIN-

PART

OUTPUTS

Automatic Self-Configuration at Power-Up

from Internal EEPROM Memory

RANGE

PACKAGE

MAX24305EXG+

MAX24310EXG+

-40 to +85

81-CSBGA

Uses External Crystal, Oscillator or Clock

Signal As Master Clock

+Denotes a lead(Pb)-free/RoHS-compliant package.

Internal Compensation for Local Oscillator

Frequency Error

♦

SPI Processor Interface

1.8V + 3.3V Operation (5V Tolerant)

-40°C to +85°C Operating Temp. Range

10mm x 10mm CSBGA Package

12 3 4

中文翻译

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