MAX20343/MAX20344
Ultra-Low Quiescent Current,
Low Noise 3.5W Buck-Boost Regulator
Absolute Maximum Ratings
IN, OUT, SDA, SCL, EN, FAST, RSEL,
FC2QFN) (derate 17.04mW/°C above +70°C).......1363.20mW
Operating Temperature Range
PGOOD, INGOOD, INT, CAP............................ -0.3V to +6.0V
LVLX...............................................................-0.3V to V + 0.3V
MAX20343.........................................................-40°C to +85°C
MAX20344.......................................................-40°C to +125°C
Junction Temperature.......................................................+150°C
Storage Temperature Range ..............................-40°C to +150°C
Soldering Temperature (reflow) ........................................+260°C
IN
HVLX .........................................-0.3 to min(V
+ 0.3V, +6.0V)
OUT
Continuous Power Dissipation (Multilayer Board,
= +70°C) (4 x 4 Array 16-Ball, 1.77mm x 2.01mm, 0.4mm..
T
A
Pitch WLP) (derate 17.26mW/°C above +70°C)....1380.80mW
Continuous Power Dissipation (Multilayer Board,
T
A
= +70°C) (12-Pin, 2.50mm x 2.50mm, 0.5mm Pitch ...........
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the
device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Package Information
16-BUMP WLP
Package Code
W161C2+1
Outline Number
21-100328
Land Pattern Number
Refer to Application Note 1891
THERMAL RESISTANCE, SINGLE-LAYER BOARD
Junction-to-Ambient (θ
)
JA
Junction-to-Case Thermal Resistance (θ
)
JC
THERMAL RESISTANCE, FOUR-LAYER BOARD
Junction-to-Ambient (θ
)
JA
57.93°C/W
12-Pin FC2QFN
Package Code
F122B2F+1
Outline Number
21-100331
90-100130
Land Pattern Number
THERMAL RESISTANCE, SINGLE-LAYER BOARD
Junction-to-Ambient (θ
)
JA
Junction-to-Case Thermal Resistance (θ
)
JC
THERMAL RESISTANCE, FOUR-LAYER BOARD
Junction-to-Ambient (θ
)
JA
58.70°C/W
23.10°C/W
Junction-to-Case Thermal Resistance (θ
)
JC
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages.
Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different
suffix character, but the drawing pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a
four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/
thermal-tutorial.
www.maximintegrated.com
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