Hig h -Fre q u e n c y Wa ve fo rm Ge n e ra t o r
MAX038
charge C , so the rate at which V
loop bandwidth) is inversely proportional to C
changes (the
PD
FADJ
+5V -5V
C1
1µF
.
PD
C2
1µF
The phase error (deviation from phase quadrature)
depends on the open-loop gain of the PLL and the ini-
tial frequency deviation of the oscillator from the exter-
14 16 17 20
4
CENTER
SYNC DV+ V+ V- A1
REF
FREQUENCY
3
nal signal source. The oscillator conversion gain (K ) is:
o
1
7
A0
K
= ∆ω
∆VF
[17]
[18]
[19]
O
ADJ
o ÷
R
D
which, from equation [6] is:
= 3.43 x ω (radians/sec)
DADJ
R
OUT
50Ω
19
10
8
K
O
o
IIN
OUT
MAX038
RF
OUTPUT
The loop gain of the PLL system (K ) is:
FADJ
V
K = K x K
O
V
D
R
PD
where:
13
12
PDI
5
K
D
= detector gain
= oscillator gain.
O
COSC
PDO
C
PD
C
F
K
GNDGND GND GND GNDDGND
11 18 15
2
6
9
With a loop filter having a response F(s), the open-loop
transfer function, T(s), is:
T(s) = K x K x F(s) ÷ s
[20]
D
O
EXTERNAL OSC INPUT
Using linear feedback analysis techniques, the closed-
loop transfer characteristic, H(s), can be related to the
open-loop transfer function as follows:
H(s) = T(s) ÷ [1+ T(s)]
[21]
Figure 3. Phase-Locked Loop Using Internal Phase Detector
The transient performance and the frequency response
of the PLL depends on the choice of the filter charac-
teristic, F(s).
PDO is a rectangular current-pulse train, alternating
between 0µA and 500µA. It has a 50% duty cycle when
the MAX038 output and PDI are in phase-quadrature
(90° out of phase). The duty cycle approaches 100%
as the phase difference approaches 180° and con-
ve rs e ly, a p p roa c he s 0% a s the p ha s e d iffe re nc e
When the MAX038 internal phase detector is not used,
PDI and PDO should be connected to GND.
External Phase Detectors
External phase detectors may be used instead of the
internal phase detector. The external phase detector
shown in Figure 4 duplicates the action of the MAX038’s
internal phase detector, but the optional ÷N circuit can
be placed between the SYNC output and the phase
detector in applications requiring synchronizing to an
exact multiple of the external oscillator. The resistor net-
work consisting of R4, R5, and R6 sets the sync range,
while capacitor C4 sets the capture range. Note that
this type of phase detector (with or without the ÷N cir-
cuit) locks onto harmonics of the external oscillator as
well as the fundamental. With no external oscillator
input, this circuit can be unpredictable, depending on
the state of the external input DC level.
approaches 0°. The gain of the phase detector (K )
D
can be expressed as:
K
D
= 0.318 x R (volts/radian)
[16]
PD
where R = phase-detector gain-setting resistor.
PD
When the loop is in lock, the input signals to the phase
detector are in approximate phase quadrature, the duty
cycle is 50%, and the average current at PDO is 250µA
(the c urre nt s ink of FADJ ). This c urre nt is d ivid e d
between FADJ and R ; 250µA always goes into FADJ
PD
and any difference current is developed across R
,
PD
creating V
(both polarities). For example, as the
FADJ
phase difference increases, PDO duty cycle increases,
the average current increases, and the voltage on R
PD
(a nd V
) b e c ome s more p os itive . This in turn
FADJ
Figure 4 shows a frequency phase detector that locks
onto only the fundamental of the external oscillator.
With no external oscillator input, the output of the fre-
quency phase detector is a positive DC voltage, and
the oscillations are at the lowest frequency as set by
R4, R5, and R6.
decreases the oscillator frequency, reducing the phase
difference, thus maintaining phase lock. The higher
R
is, the greater V
is for a given phase differ-
PD
FADJ
ence; in other words, the greater the loop gain, the less
the capture range. The current from PDO must also
______________________________________________________________________________________ 13
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