19-1236; Rev 0; 6/97
Lo w -P o w e r, 9 0 Ms p s , Du a l 6 -Bit ADC
MAX103
_______________Ge n e ra l De s c rip t io n
____________________________Fe a t u re s
♦ Two Matched 6-Bit ADCs
The MAX1003 is a dual, 6-bit analog-to-digital converter
(ADC) that combines high-speed, low-power operation
with a user-selectable input range, an internal refer-
ence, and a clock oscillator. The dual parallel ADCs are
designed to convert in-phase (I) and quadrature (Q)
analog signals into two 6-bit, offset-binary-coded digital
outputs at sampling rates up to 90Msps. The ability to
directly interface with baseband I and Q signals makes
the MAX1003 ideal for use in direct-broadcast satellite,
VSAT, and QAM16 demodulation applications.
♦ High Sampling Rate: 90Msps per ADC
♦ Low Power Dissipation: 350mW
♦ Excellent Dynamic Performance:
5.85 ENOB with 20MHz Analog Input
5.7 ENOB with 50MHz Analog Input
♦ ±1/4LSB INL and DNL (typ)
♦ Internal Bandgap Voltage Reference
♦ Internal Oscillator with Overdrive Capability
The MAX1003 input amplifiers feature true differential
inputs, a -0.5dB analog bandwidth of 55MHz, and user-
programmable input full-scale ranges of 125mVp-p,
250mVp-p, or 500mVp-p. With an AC-coupled input
signal, matching performance between input channels
is typically better than 0.1dB gain, 1/4LSB offset, and
0.5° phase. Dynamic performance is 5.85 effective
number of bits (ENOB) with a 20MHz analog input sig-
nal, or 5.7 ENOB with a 50MHz signal.
♦ 55MHz (-0.5dB) Bandwidth Input Amplifiers with
True Differential Inputs
♦ User-Selectable Input Full-Scale Range
(125mVp-p, 250mVp-p, or 500mVp-p)
♦ 1/4LSB Channel-to-Channel Offset Matching (typ)
♦ 0.1dB Gain and 0.5° Phase Matching (typ)
♦ Single-Ended or Differential Input Drive
The MAX1003 operates with +5V analog and +3.3V digi-
tal supplies for easy interfacing to +3.3V-logic-compati-
ble digital signal processors and microprocessors. It
comes in a 36-pin SSOP package.
♦ Flexible, 3.3V, CMOS-Compatible Digital Outputs
________________________Ap p lic a t io n s
Direct Broadcast Satellite (DBS) Receivers
VSAT Receivers
______________Ord e rin g In fo rm a t io n
PART
TEMP. RANGE
PIN-PACKAGE
Wide Local Area Networks (WLANs)
Cable Television Set-Top Boxes
MAX1003CAX
0°C to +70°C
36 SSOP
Pin Configuration appears at end of data sheet.
_________________________________________________________Fu n c t io n a l Dia g ra m
IOCC+
IOCC-
IIN+
IIN-
INPUT
AMP
I
6
6
ADC
I
VREF
DI0–DI5
DCLK
DATA
BUFFER
I
OFFSET
CORREC-
TION I
CLOCK
OUT
TNK+
TNK-
GAIN
BANDGAP
REFERENCE
CLOCK
DRIVER
OFFSET
CORREC-
TION Q
MAX1003
QIN+
QIN-
VREF
ADC
6
DATA
BUFFER
Q
INPUT
AMP
Q
6
DQ0–DQ5
Q
QOCC+
QOCC-
________________________________________________________________ Maxim Integrated Products
1
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