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MAS3690CB

更新时间： 2024-11-14 20:01:43
品牌 Logo 应用领域
DYNEX 通信时钟数据传输外围集成电路
页数 文件大小 规格书
41页 424K
描述
Mil-Std-1553 Controller, 2 Channel(s), 0.125MBps, CMOS, CDIP48

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MAS3690CB 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：DIP, DIP48,.6Reach Compliance Code：unknown
HTS代码：8542.31.00.01风险等级：5.92
其他特性：DUAL BUS CAPABILITY; MA3690 & MA3691 IS A CHIP SET OF 1553B BUS CONTROLLER/REMOTE TERMINAL地址总线宽度：2
边界扫描：NO最大时钟频率：12 MHz
通信协议：MIL-STD-1553B数据编码/解码方法：BIPH-LEVEL(MANCHESTER)
最大数据传输速率：0.125 MBps外部数据总线宽度：16
JESD-30 代码：R-CDIP-T48JESD-609代码：e0
低功率模式：NODMA 通道数量：
I/O 线路数量：串行 I/O 数：2
端子数量：48片上数据RAM宽度：
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：DIP
封装等效代码：DIP48,.6封装形状：RECTANGULAR
封装形式：IN-LINE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 V认证状态：Not Qualified
RAM（字数）：0筛选级别：38535Q/M;38534H;883B
子类别：Serial IO/Communication Controllers最大压摆率：25 mA
最大供电电压：5.5 V最小供电电压：4.5 V
标称供电电压：5 V表面贴装：NO
技术：CMOS温度等级：MILITARY
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIEDuPs/uCs/外围集成电路类型：SERIAL IO/COMMUNICATION CONTROLLER, MIL-STD-1553
Base Number Matches：1

MAS3690CB 数据手册

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MA3690/1/3  
1553B Bus Controller/Remote Terminal  
Replaces June 1999 version, DS3587-4.0  
DS3587-5.0 January 2000  
The MA3690/1 chip set has three modes of operation:  
remote terminal, bus controller, and passive monitor It has a  
dual bus capability, requires minimum support hardware /  
software and is implemented on a radiation hard, CMOS/SOS  
process. For applications requiring access to Terminal Flag, a  
48-Pin DIL MA3693 is available as an alternative to the  
MA3690.  
As a remote terminal, the MA3690/1 is fully compatible with  
Mil-Std-1553B. The chip set obtained SEAFAC approval in  
December 1987. All options and mode commands specified by  
the Mil Std are implemented Full and meaningful use is made  
of status word bits and a comprehensive bit word is provided.  
A unique mechanism has been incorporated that allows  
the subsystem to declare illegal commands legal, and vice  
versa, before the chip set services the command. It should be  
noted that use of this mechanism is optional and that the  
system defaults to normal operation if the option is not  
required. The chip set is easily interfaced to subsystem  
memory and is sufficiently flexible to ensure compatibility with  
a wide range of microprocessors.  
FEATURES  
■ Radiation Hard to 1MRads (Si)  
■ High SEU Immunity, Latch-Up Free  
■ CMOS-SOS Technology  
■ All Inputs and Outputs Fully TTL or CMOS Compatible  
■ Military Temperature Range -55 to +125°C  
■ Dual Bus Capability  
■ Minimal Subsystem Interface  
■ Powerful Bus Control Facility  
■ Complete Remote Terminal Protocol  
■ SEAFAC Approved  
SIGNAL DESCRIPTIONS  
All signals are TTL compatible unless stated otherwise. An  
‘N’ at the end of the signal name denotes an active low signal.  
As a bus controller the MA3690/1 has the ability to initiate  
all types of 1553B transfer on either of the two buses An  
instruction word is set up by the subsystem, prior to  
transmission, which contains details of transfer type and bus  
selection. Four bits of the instruction word have been used to  
specify the conditions under which the chip set will generate a  
subsystem interrupt. The most significant bits of the instruction  
word have been used to specify the conditions under which the  
chip set will perform an automatic retry and the number of  
retries to be carried out (max. 3). At the end of each instruction  
execution cycle, the chip set writes a report word into the  
subsystem memory; the contents of which give the subsystem  
an indication of the degree of success of the transfer.  
The bus controller may be used in either of two  
configurations, i.e. single shot or table driven.  
SUPPLIES  
VDD  
VSS  
5 volts positive supply  
Ground  
CLOCK INPUTS  
CK12  
12MHz clock  
BUS INTERFACE LINES  
In the single shot configuration, the controller is under  
direct control from the subsystem (processor). In table driven  
configuration, the controller is given greater autonomy to  
execute a table of instructions held in either ROM or RAM.  
As a passive monitor, the chip set will monitor all bus  
activity and pass any associated information to the subsystem.  
As the name implies, in this mode of operation, the chip set is  
truly passive and will not reply to command instructions.  
PDIN0  
Input  
Positive threshold exceeded on bus 0.  
NDIN0  
Input  
Negative threshold exceeded on bus 0.  
TXEN0N  
Output  
Transmit enable for driver on bus 0.  
PDOUT0N  
Output  
Positive Manchester data for driver on bus 0.  
1/41  
1234567...41

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 		1553B Bus Controller/Remote Terminal
MAS3690CD DYNEX

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 		1553B Bus Controller/Remote Terminal
MAS3690CE DYNEX

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 		1553B Bus Controller/Remote Terminal
MAS3690CL DYNEX

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 		1553B Bus Controller/Remote Terminal
MAS3690FC DYNEX

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 		1553B Bus Controller/Remote Terminal
MAS3690FD DYNEX

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 		1553B Bus Controller/Remote Terminal
MAS3690FE DYNEX

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 		1553B Bus Controller/Remote Terminal
MAS3690FL DYNEX

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 		1553B Bus Controller/Remote Terminal
MAS3690NB DYNEX

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 		Mil-Std-1553 Controller, 2 Channel(s), 0.125MBps, CMOS, DIE
MAS3690NC DYNEX

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 		1553B Bus Controller/Remote Terminal

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