Datasheet > M82C288-10

M82C288-10

更新时间： 2024-02-22 14:45:45

品牌	Logo	应用领域
英特尔 - INTEL		控制器
页数	文件大小	规格书
20页	329K
描述
BUS CONTROLLER FOR M80286 PROCESSORS

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M82C288-10 数据手册

M82C288

Bus cycles can occur back to back with no T bus

states between T and T . Back to back cycles do

not affect the timing of the command and control

outputs. Command and control outputs always

reach the states shown for the same clock edge

(within T , T or following bus state) of a bus cycle.

A special case in control timing occurs for back to

back write cycles with MB

0. In this case, DT/R

and DEN remain HIGH between the bus cycles (see

Figure 8). The command and ALE output timing

does not change.

Figures 9 and 10 show a MULTIBUS I cycle with MB

1. AEN and CMDLY are connected to GND. The

effects of CMDLY and AEN are described later in

the section on control inputs. Figure 9 shows a read

cycle with one wait state and Figure 10 shows a

write cycle with two waits states. The second wait

state of the write cycle is shown only for example

purposes and is not required. The READY input is

shown to illustate how wait states are added.

271077–8

Figure 8. Write-Write Bus Cycles with MB

271077–9

Figure 9. Idle-Read-Idle Bus Cycles with 1 Wait State and with MB

1...5 6 789 10 11...20

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