Datasheet > M82C288-10

M82C288-10

更新时间： 2024-02-05 04:54:22

品牌	Logo	应用领域
英特尔 - INTEL		控制器
页数	文件大小	规格书
20页	329K
描述
BUS CONTROLLER FOR M80286 PROCESSORS

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M82C288-10 数据手册

M82C288

Figures 6 through 10 show the basic command and

control output timing for read and write bus cycles.

Halt bus cycles are not shown since they activate no

outputs. The basic idle-read-idle and idle-write-idle

bus cycles are shown. The signal label CMD repre-

sents the appropriate command output for the bus

cycle. For Figures 6 through 10, the CMDLY input is

CENL and CMDLY are described later in the section

on control inputs.

Figures 6, 7, and 8 show non-MULTIBUS I cycles.

MB is cnonected to GND while CEN is connected to

. Figure 6 shows a read cycle with no wait states

while Figure 7 shows a write cycle with one wait

state. The READY input is shown to illustrate how

wait states are added.

connected to GND and CENL to V . The effects of

271077–6

Figure 6. Idle-Read-Idle Bus Cycles with MB

271077–7

Figure 7. Idle-Write-Idle Bus Cycles with MB

1...4 5 678 9 10...20

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