Advanced v0.7
®
Fusion Family of Mixed-Signal Flash FPGAs
®
with Optional Soft ARM Support
–
Frequency: Input (1.5–350 MHz), Output (0.75–350 MHz)
Features and Benefits
High Performance Reprogrammable
Flash Technology
Low Power Consumption
•
•
Single 3.3 V Power Supply with On-Chip 1.5 V Regulator
Sleep and Standby Low Power Modes
•
•
•
•
Advanced 130-nm, 7-Layer Metal, Flash-Based CMOS Process
Nonvolatile, Retains Program When Powered-Off
Live at Power-Up (LAPU) Single-Chip Solution
350 MHz System Performance
In-System Programming (ISP) and Security
•
•
Secure ISP with 128-Bit AES Via JTAG
®
FlashLock to Secure FPGA Contents
Advanced Digital I/O
Embedded Flash Memory
•
•
•
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Bank-Selectable I/O Voltages – Up to 5 Banks per Chip
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V /
1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X and LVCMOS 2.5 V / 5.0 V
Input
•
User Flash Memory – 2 Mbits to 8 Mbits
–
–
Configurable 8-, 16-, or 32-Bit Datapath
10 ns Access in Read-Ahead Mode
•
1 kbit of Additional FlashROM
Integrated A/D Converter (ADC) and Analog I/O
•
Differential I/O Standards: LVPECL, LVDS, BLVDS, and M-LVDS
•
•
•
•
•
•
Up to 12 bit resolution and Up to 600 ksps
Internal 2.56 V or External Reference Voltage
ADC: Up to 30 Scalable Analog Input Channels
High Voltage Input Tolerance 12 V
Current Monitor and Temperature Monitor Blocks
Up to 10 MOSFET Gate Driver Outputs
–
–
Built-In I/O Registers
700 Mbps DDR Operation
•
•
Hot-Swappable I/Os
Programmable Output Slew Rate, Drive Strength, and Weak
Pull-Up/Down Resistor
•
Pin-Compatible Packages Across the Fusion Family
–
–
P- and N-Channel Power MOSFET support
Programmable 1, 3, 10, 30 µA and 25 mA Drive Strengths
SRAMs and FIFOs
•
Variable-Aspect-Ratio 4,608-Bit SRAM Blocks (x1, x2, x4, x9,
and x18 organizations available)
On-Chip Clocking Support
•
•
•
•
Internal 100 MHz RC Oscillator (accurate to 1%)
Crystal Oscillator Support (32 kHz to 20 MHz)
Programmable Real-Time Counter (RTC)
•
•
True Dual-Port SRAM (except x18)
Programmable Embedded FIFO Control Logic
Soft ARM7™ Core Support in M7 Fusion Devices
6 Clock Conditioning Circuits (CCCs) with 1 or 2 Integrated PLLs
•
CoreMP7Sd (with debug) and CoreMP7S (without debug)
–
Phase Shift, Multiply/Divide, and Delay Capabilities
Table 1 • Fusion Family
Fusion Devices
AFS090
AFS250
AFS600
AFS1500
ARM-Enabled Fusion Devices
System Gates
M7AFS600
M7AFS1500
90,000
2,304
250,000
6,144
600,000
13,824
7,500
5,237
Yes
1,500,000
38,400
32,000
29,878
Yes
Tiles (D-Flip-Flops)
Usable Tiles with CoreMP7S
1
General
Information
1
Usable Tiles with CoreMP7Sd
Secure (AES) ISP
PLLs
Yes
1
Yes
1
2
2
Globals
18
1
18
1
18
18
Flash Memory Blocks (2 Mbits)
Total Flash Memory Bits
FlashROM Bits
2
4
2 M
1 k
6
2 M
1 k
8
4 M
1 k
8 M
1 k
Memory
RAM Blocks (4,608 bits)
RAM kbits
24
60
27
5
36
6
108
10
270
10
Analog Quads
Analog Input Channels
Gate Driver Outputs
I/O Banks (+ JTAG)
15
5
18
6
30
30
10
10
Analog and I/Os
4
4
5
5
2
Maximum Digital I/Os
75
20
114
24
172
40
252
40
Analog I/Os
Notes:
1. Refer to the CoreMP7 datasheet for more information.
2. Some debug tools require 10 digital I/Os for external connection.
October 2007
i
© 2007 Actel Corporation
See the Actel website for the latest version of the datasheet.
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