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M74HCT533TTR PDF预览

M74HCT533TTR

更新时间: 2024-11-23 19:48:47
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
11页 247K
描述
HCT SERIES, 8-BIT DRIVER, INVERTED OUTPUT, PDSO20, TSSOP-20

M74HCT533TTR 技术参数

生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP20,.25针数:20
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.26系列:HCT
JESD-30 代码:R-PDSO-G20长度:6.5 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.006 A位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP20,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL电源:5 V
Prop。Delay @ Nom-Sup:45 ns传播延迟(tpd):56 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
宽度:4.4 mmBase Number Matches:1

M74HCT533TTR 数据手册

 浏览型号M74HCT533TTR的Datasheet PDF文件第2页浏览型号M74HCT533TTR的Datasheet PDF文件第3页浏览型号M74HCT533TTR的Datasheet PDF文件第4页浏览型号M74HCT533TTR的Datasheet PDF文件第5页浏览型号M74HCT533TTR的Datasheet PDF文件第6页浏览型号M74HCT533TTR的Datasheet PDF文件第7页 
M74HCT533  
OCTAL D-TYPE LATCH  
WITH 3 STATE OUTPUT INVERTING  
HIGH SPEED:  
=20ns (TYP.) at V = 4.5V  
t
PD  
CC  
LOW POWER DISSIPATION:  
= 4µA(MAX.) at T =25°C  
I
CC  
A
COMPATIBLE WITH TTL OUTPUTS :  
= 2V (MIN.) V = 0.8V (MAX)  
V
IH  
IL  
DIP  
SOP  
TSSOP  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 6mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
ORDER CODES  
PACKAGE  
PLH  
PHL  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 533  
TUBE  
T & R  
DIP  
SOP  
M74HCT533B1R  
M74HCT533M1R M74HCT533RM13TR  
M74HCT533TTR  
DESCRIPTION  
The M74HCT533 is an high speed CMOS OCTAL  
LATCH WITH 3-STATE OUTPUTS fabricated  
TSSOP  
2
with silicon gate C MOS technology.  
level) and while high level the outputs will be in a  
high impedance state.  
The 3-State output configuration and the wide  
choice of outline make bus organized system  
simple.  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
This 8-BIT D-Type latches is controlled by a latch  
enable input (LE) and output enable input (OE).  
While the LE input is held at a high level, the Q  
outputs will follow the data input inversely. When  
LE is taken low, the Q outputs will be latched  
inversely at the logic level of D input data.  
While the OE input is at low level, the eight outputs  
will be in a normal logic state (high or low logic  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
August 2001  
1/11  

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