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M74HCT273C1R PDF预览

M74HCT273C1R

更新时间: 2024-11-18 22:35:43
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 触发器锁存器逻辑集成电路
页数 文件大小 规格书
10页 246K
描述
OCTAL D TYPE FLIP FLOP WITH CLEAR

M74HCT273C1R 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QFN包装说明:PLASTIC, CC-20
针数:20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.74
Is Samacsys:N系列:HCT
JESD-30 代码:S-PQCC-J20JESD-609代码:e3
长度:8.9662 mm负载电容(CL):50 pF
逻辑集成电路类型:D FLIP-FLOP最大频率@ Nom-Sup:24000000 Hz
最大I(ol):0.004 A位数:8
功能数量:1端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC20,.4SQ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
传播延迟(tpd):38 ns认证状态:Not Qualified
座面最大高度:4.57 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:8.9662 mm最小 fmax:24 MHz
Base Number Matches:1

M74HCT273C1R 数据手册

 浏览型号M74HCT273C1R的Datasheet PDF文件第2页浏览型号M74HCT273C1R的Datasheet PDF文件第3页浏览型号M74HCT273C1R的Datasheet PDF文件第4页浏览型号M74HCT273C1R的Datasheet PDF文件第5页浏览型号M74HCT273C1R的Datasheet PDF文件第6页浏览型号M74HCT273C1R的Datasheet PDF文件第7页 
M54HCT273  
M74HCT273  
OCTAL D TYPE FLIP FLOP WITH CLEAR  
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HIGH SPEED  
fMAX = 80 MHz (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) AT TA = 25 °C  
COMPATIBLE WITH TTL OUTPUTS  
VIH = 2V (MIN.) VIL = 0.8V (MAX)  
OUTPUT DRIVE CAPABILITY  
10 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
IOH = IOL = 4 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
PIN AND FUNCTION COMPATIBLE WITH  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
54/74LS273  
ORDER CODES :  
DESCRIPTION  
M54HCT273F1R  
M74HCT273M1R  
M74HCT273B1R  
M74HCT273C1R  
The M54/74HCT273 isa high speed CMOS OCTAL  
D-TYPE FLIP FLOP WITH CLEAR fabricated in sili-  
con gate C2MOS technology. It has the same high  
speed performance of LSTTL combined with true  
CMOS low power consumption. Information signals  
applied to D inputs are transferred to the Q outputs  
on the positive-going edge of the clock pulse.  
When the CLEAR input is held low, the Q output are  
in the low logic level independent of the other inputs.  
All inputs are equipped with protection circuits  
against static discharge and transient excess volt-  
age. This integrated circuit has input and output  
characteristics that are fully compatible with 54/74  
LSTTL logic families. M54/74HCT devices are de-  
signed to directly interface HSC2MOS systems with  
TTL and NMOS components. They are also plug in  
replacements for LSTTL devices giving a reduction  
of power consumption. All inputs are equipped with  
protection circuits against static discharge and tran-  
sient excess voltage.  
PIN CONNECTIONS (top view)  
INPUT AND OUTPUT EQUIVALENT CIRCUIT  
NC =  
No Internal  
Connection  
February 1993  
1/10  

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